Tommy Thorn
tommythorn@chaos.social
Imagine RISC-V but where every immediate has two more bits and branches/jumps can reach 8X as far? #RISCV what could have been and should be.
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Tommy Thorn
tommythorn@chaos.socialIn fairness, I’d have designed the ISA such that *all* instructions taking an rs2 has an immediate variant version. And sub should have been rsub, allowing, eg 1-x in one insn.
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@tommythorn or, you know, just make the architecture two-operand for integer instructions where the destructive write isn’t a big deal. That’s several bits for everything right there, not just immediates.
The same people who hate on two-operand architectures (“oh, no, destructive source”) often then think FORTH is cool. Strange.
(And yes, FORTH is cool. I’m just saying that there is a mental disconnect with the whole destructive source thing. The occasional “mov” instruction is no worse than a “dup” or “over”)
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