Today is a good day.

@azonenberg neat, are those (fpga?) boards with the SATA data connectors for matched length cabling?

@xabean I assume they're GTX breakouts but not sure, I was sent the chips to decap. They're -1 speed Kintex-7's that I have no use for.

The XCKU5P in the background was purchased cheap on aliexpress but so far appears legit.

One of the items in this shipment is (allegedly) a Xilinx XCKU5P that was cheap on AliExpress. The guy who sent it to me did some preliminary dead bug proof of life testing so now it's got bypass caps and missing solder balls stuck to the bottom.

Let's clean it up.

Doing a full chip bottom side substrate scan of the XCKU5P-2FFVB676I on the Labsmore X1.

I don't have a proper darkfield setup but find that pure metallurgical brightfield illumination works poorly on chip packages and PCBs. Here's the low angle LED lamp setup I'm experimenting with.

Hard to get good uniformity on larger samples but it works decently.

Bottom side substrate photo, mirrored so it lines up with the top-down view in the datasheet. Ball A1 in top left corner. Slightly overexposed on the top left but it'll do.

A few of the lands look to have small amounts of solder residue that I didn't quite clean off fully, so before I reball I'll inspect and possibly clean them up. Hard to tell exactly how much solder there is in this lighting.

There's also a scratch in the soldermask around the T-U 12-13 region. Shouldn't be a big problem but I might try to touch it up just to make sure I don't get any problems.

The substrate matches the ballout perfectly (further evidence the chip is real) although there are a few interesting things:

* The GTY refclks don't have ground plane cutouts around them for impedance matching, only the high speed SERDES

* There's a tiny single-pin ground island next to the VCCAUX_IO island. Why not just fill with VCCINT there?

* Most interestingly, the VCCO zone fills don't line up with the IO banks!

For example, on the substrate the VCCO_66 zone fill is a rectangle spanning A21 to J26.

But A21-A25 are in bank 67, not bank 66! So a significant number of the IOs surrounded by VCCO_66 are not actually powered by VCCO_66.

I wonder why this was done?

@azonenberg Also interesting that bank 0 (config) is in the GTY ground fill.

@dlharmon Maybe they figured you won't be booting and using the GTYs simultaneously so no issues there?

But bank 0 is usable at runtime for storing user data in flash etc.

@azonenberg Probably a non-issue with that wall of ground vias between that and GTY, I'm just surprised they didn't treat that just like the HD banks.

@dlharmon Yeah me too.

CORRECTION: this is FFVB676 not FFVA676, but I don't seem to be able to edit alt text. Oops.

Side view of the package substrate. It's a fourteen layer board!

The overall construction is two sets of seven layers using very thin, light colored dielectric with no evident glass reinforcement (so likely some kind of fancy microwave laminate) on either side of a thick core using a more conventional woven glass-resin structure.

The glass in the core looks to be spread but it's otherwise unremarkable.

@azonenberg Wow, those layers are really closely bunched up. Probably to increase coupling so that impedance controlled tracks can be much narrower? Interesting stuff

@gnarf I mean they're fanning out 676 signals from a die with tight pitch solder bumps to a 27x27mm BGA array. There's not much space to work with so you need your tracks to be thin.

And with DDR4 2667 and 32 Gbps SERDES support in the highest speed grade impedance control isn't an option, it's absolutely mandatory.

Without knowing the Dk of the substrate hard to be sure but I expect 50 ohm traces are 50um or less in width.

Ok so, I need to reball this thing and my supplies are coming later today.

Before I reflow it I should probably try to desiccate it a bit more though.

IPC guidelines seem to suggest I should bake for 9 hours at 125C but that's probably not practical given that my oven only runs for a max of an hour at a time and so I'd need to be around to reset every hour. But I'll do as many 1-hour cycles as I have time for before I reball tonight.

@azonenberg I don't suppose using a discarded kitchen oven has the precision that this requires?

@purpleidea I'm actually using a toaster oven, but one dedicated to lab usage that's never had food in it.

@azonenberg It doesn't never have to have had food in it, it just should never have food in it afterwards =D

#pizzaflavouredcircuitboards

@purpleidea Lol. I don't want pizza grease and crumbs on my PCBs. Better to separate both from the beginning.

@azonenberg
How hot does the bed of your 3d printer get?

@FritzAdalis Not a clue, ask Shapeways.

3D printing is one of those things that I do infrequently and with different requirements each time, so it makes more sense to outsource to someone who can do SLA one day and MJF the next and SLS the next, rather than trying to shoehorn all of my work into a single process.

Also I'm very tight on lab space so if I don't absolutely need quick turn or hands-on access for debugging, I prefer to outsource capabilities. Same reason I don't etch even trivial 1-layer breakout PCBs here.

On something like the third or fourth hour of baking the FPGA. Threw in a desiccant pouch to reactivate it since I couldn't find any unused desiccant other than loose silica gel beads.

I think this one was pretty saturated, lol. My lab is around 37% RH right now which is lowish but clearly not low enough.

Reballing fixture and 676 ball 1mm preforms came in.

I'll let the chip cook a bit more before reballing it as I'm not in a rush.

These are pretty cool and it's my first time using them although I've been aware of them for quite a while. Instead of using loose solder balls you just flux the entire chip and stick this preform on top of it then reflow upside down to attach the balls.

You then apply a bit of water to soften the carrier material and it comes off leaving perfectly positioned solder balls.

Definitely more expensive than doing it with a stencil and loose balls (I paid a few hundred bucks for the fixture and 25 preforms) but IMO worth it for salvaging pricier parts.

Welp. Guess I'm not using this desiccant.

Bag melted all over my tray and leaked.

It said right on the pouch to recharge at 245F and that's what I had the oven set for :(

On the plus side I found another pack of desiccant in the office of all places. So i can still dry pack it.

@azonenberg If it's a food oven, my experience is that their temperature control is rather aspirational, especially if not in convection mode

@lcamtuf I've profiled this pretty carefully for soldering (in convection mode).

But I don't have as much characterization data at lower temperature ranges (i.e. 100C vs 250C).

Also, it's entirely possible that the plastic got hotter than the air from IR off the heating elements because it has so little thermal mass.

@ChuckMcManis Yeah I reflow boards in this all the time and I know it works well at higher temp ranges.

The oven was hot already when I put the desiccant in. My guess is maybe IR heating caused some of the plastic to get hotter than the air or something.

Ok, reballing time.

Quick visual inspection of the preform under the microscope to make sure nothing is missing. Looks good.

After putting the preform in the fixture (ball side up) all I need to do is smear flux evenly across the lands on the package (no photos since my gloves were all sticky) and put the FPGA on top.

Then off to the oven.

Here goes.

I normally gauge BGA reflow by watching the solder turn shiny and the chip drop, but that's not possible in this setup.

So I squirted some SAC305 paste on a witness board next to the fixture and gave it about 45 seconds after that melted. Hopefully it was enough, we'll find out when it cools.

@azonenberg@ioc.exchange Were you having a ball while doing this?

@mrhamel No, I was having many balls. 676 of them, to be precise.

No go, it didn't attach. I guess that's better than overcooking and damaging the FPGA?

Back in the oven for another round.

This time I added witness solder on Kapton tape pads on both the FPGA package and the fixture. They melted quite a bit later than the adjacent board did.

Gave it 45 sec after *they* melted and hopefully it's good. I don't want to put more thermal cycles on this chip than I have to. I've already violated the absolute max ratings enough :)

Welp. I don't think they're supposed to do that.

OK, cleaned up the gunk and re-tinned the pads with an iron (in case there were any issues with residue or something).

Time to try again.

This time on a scrap PCB to prevent any weirdness from the ridged tray I had it on last time. Maybe a bit more generous on the flux too?

Here we go again.

Wonder if it'll work after all this? Good practice if nothing else I guess.

No go same failure mode. Preform expanded and sagged away from the BGA causing center balls to not make contact.

This chip might end up becoming microscope food. I'll play with it more but it's been through a lot of oven cycles now.

Cleaned off the paper, looks like a bunch of the balls around the edges did attach OK.

I wonder if my problem is not enough airflow under the chip? They do talk about that being important in the other process guidelines I found after some more research.

Maybe instead of putting this on a solid tray I should try putting it on the wire oven rack directly or something.

@azonenberg this might be a stupid question, but why can't you reflow it with the chip upside down with the preform on top?

@xabean The directions say not to :)

But I'm willing to try if I run out of other ideas.

@xabean Process guidelines suggest airflow under the preform is important so that's going to be my next try.

@azonenberg >instead of putting this on a solid tray I should try putting it on the wire oven rack

I'd say worth a shot, something about that solid tray makes me feel like the convection airflow is restricted in the areas below the chip, the two lanes its propped up on may lead to the edges making contact to heat up quicker than the center of the chip, right? centering the chip on one of the lanes could help too but ehhh I'd shoot for the wire rack, let it "float" in that toasty-warm air.

@haifisch Yeah usually I use it on 2 sided reflow where it's fine if the bottom side is a little cooler than the top.

@azonenberg oh true, it does act like a heatsink, I was thinking inverse effect was happening half facepalming lolol. smaller tray /could/ help but meh. another whacky idea is metal wire and making a little support grid using hex standoffs and attach the standoffs to the oven wire rack. maybe titanium wire if its not too pricey?

also I just noticed, is that an oshpark pcb you're using as a bed? love them!

@haifisch All of my smaller 4 layer prototypes are done on oshpark.

I've just moved to fancier fabs for the 10 layer monsters I do for my big projects now

Ok last try for today.

@azonenberg and you're sure it's not supposed to be done upside down?

@mattieuMattieu The instructions are very clear that it is supposed to be right side up. There's a big picture of a chip ball side up with preform on top captioned "WRONG WAY"

@azonenberg wouldn't that give off all that moisture into the oven?

@GyrosGeier Yes (and then sucked out by the vent). It wouldn't contaminate the chip significantly at this temperature if that's what you're thinking.

Nope same issue with preform sagging.

Tempted to try upside down, it can't be worse than the proper way right?

Or give up on preforms and do it the hard way.

@azonenberg To me it looks aligned in some places and skewing as you go across - is the substrate that holds the balls really the right pitch, or is it changing as heated?

@penguin42 The preform appears to be sagging in the center. Unclear if this is due to gravity as it softens while heated, thermal expansion, or something else. Either way it's not supposed to happen.

Actually whoops, these are 0.5mm balls and I really need 0.6 to do the job right. Ordered some as I didn't have any in stock.

Anyway, I figure it's worth trying. This chip has been through hell by this point, two of the GTY RX pads are damaged (but not completely gone - so may still make contact just mechanically less robust).

I'm now thinking of making a little OSHPark test board that basically hooks up power, JTAG, cooling, and breaks out some of the SERDES so I can play with it, but not a whole lot else. Not sure I'd trust it on the BERT (which is still happening, but likely not with this physical chip).

My balls came! 0.6mm SAC305 solder spheres, a more reasonable 25K vs the 250K jar of 0.5mm that I'll never use (not that I expect to use 25K either but hey it was cheaper).

Always interesting to see them charge up and repel when you shake the container.

And if you jiggle the jar just right they "anneal" and form a hexagonal close packed "crystal" with large grains and occasional dislocations.

Going to try reballing the KU5P tonight using these and a stencil. We'll see how it goes... good chance it'll end badly but I'm not gonna get better at reballing without practice.

Best fit stencil i had was one row of balls too small so i have to hand place the outer ring. A dozen or so stuck to the stencil when i removed it.

Tweezer time...

Took a break to let my hand rest and counted the voids while I was waiting. 63 missing balls now missing out of 676.

The other big question of course is how many will move around and need to be cleaned up post reflow... I don't expect perfect results but can hope :)

25 left and I need to stretch my hand out again. Looks like a few sections are a bit light on flux, hopefully they reflow OK.

Also found that the AF19 land still has quite a bit of solder on it, hopefully the ball doesn't move around much (or get too giant).

All done and in the oven. Here goes...

Better than I expected. No shorts or outright failures to attach. A few balls didn't self center properly due to, i think, inadequate flux.

Added more flux and reheating now. What's one more thermal cycle at this point?

I... Think it actually worked?

The only thing left to do is seal it up in a dry bag with humidity card and some desiccant, and its all ready to go on a board. Hopefully not one I care about too much although it's proooooobably fine.

Next step will be throwing together a quick OSHPark test board that provides minimal power/jtag hookups, reference clocks for the GTY quads, connectors of some sort for the GTYs, and some random GPIO breakouts.

Not a full dev board necessarily as it'll be pretty spartan (6 or even 4 layers, no RAM, etc). Goal is mostly to see if the sketchy, abused FPGA survived all this, and to validate my footprint and power supply before I make ERNIE.

It'll probably be the power supply copy pasted from ERNIE (aside from the DDR rail), a couple pmods, some breakouts for a handful of HP IOs, and breakouts for GTYs.

And some LEDs, can't forget those.

I wonder, will I be the first person insane enough to put a KU+ on a 4 layer oshpark PCB? Lol.

@azonenberg This really feels like a job for a pick-and-place like machine!

@AMS Yeah they're just big on oshpark where I get charged per square inch.

Might do a sfp28, a qsfp28, and the rest to some kind of high density connector like a Samtec q-strip.

@penguin42 if only I had one lol.

@azonenberg Nice. This is a real popular thing to do. You can get big lots of very cheap expensive FPGAs on boards from China.

@markemer Yeah this is a $3K fpga that cost $55 on aliexpress.