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Jarkko Sakkinen
jarkko
Edited 4 days ago
WebAssembly is one of the worst ideas in the industry during past 10 years. why end up with stack machine and purposely complicate JIT. Never really grabbed it engineering wise TBH but maybe I'm missing something who knows.
You don't need to be an engineer to get it. It just tends to be easier to find ways map registers to registers, and requires more stretch to move between stack and register machine.
You don't need to be an engineer to get it. It just tends to be easier to find ways map registers to registers, and requires more stretch to move between stack and register machine.
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@jarkko you would have to make assumptions about target register capabilities.. there goes your portability ? though they did make dalvik work so 🤷♀️ my beef with wasm is the lowest common denominator stuff that gets often done over
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pinkforest(she/her) 🦀
pinkforest@hachyderm.io@jarkko so dalvik got it to work with infinite-register machine so be damned with performance if it was less (slides 35, 36) http://www.kandroid.org/board/data/board/AndroidBeginner/file_in_body/1/2008-05-29-Presentation-Of-Dalvik-VM-Internals.pdf and https://markfaction.wordpress.com/2012/07/15/stack-based-vs-register-based-virtual-machine-architecture-and-the-dalvik-vm/
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pinkforest(she/her) 🦀
pinkforest@hachyderm.io@jarkko Also register liveness.. http://troubles.md/wasm-is-not-a-stack-machine/
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@pinkforest well yeah of course you need to address contraints when designing "softcore" (i guess this a term?) :-)
First, you need some register space for book keeping (like one or two registers at least) and it unfortunately shares space with softcores registers.
So problem at hand is like:
1. Reduce softcores register space i.e., it will have less registers than host CPU.
2. "Share-and-swap" registers with the softcore for the colliding part.
This of course assumes that ISA is similar enough to x86-64 and aarch64 but that is quite fair constraint to set from the get go for obvious reasons :-)
Anyhow, it will quite simple and sound translation with no artificial stack machines blocking the way :-)
First, you need some register space for book keeping (like one or two registers at least) and it unfortunately shares space with softcores registers.
So problem at hand is like:
1. Reduce softcores register space i.e., it will have less registers than host CPU.
2. "Share-and-swap" registers with the softcore for the colliding part.
This of course assumes that ISA is similar enough to x86-64 and aarch64 but that is quite fair constraint to set from the get go for obvious reasons :-)
Anyhow, it will quite simple and sound translation with no artificial stack machines blocking the way :-)
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