Conversation

Jarkko Sakkinen

Edited 1 year ago
I'm trying to get #Keystone #SM ongoing with #CVA6 but stuck with SM's trap handler giving me illegal instruction. I wonder how interpret these values for #mideleg and #medeleg: https://github.com/keystone-enclave/keystone/issues/374#issuecomment-1777032123 #riscv #opensbi
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Jarkko Sakkinen

Edited 1 year ago
I got my Genesys 2 FPGA alive with an old version, and can now conclude that either OpenSBI or SM is causing the misbehavior. It is super stressing when you don't even know whether you can get something theoretically to work, and I was in that limbo for few weeks. What a relief although work is not done yet! Was not sure whether the flashed CVA6 had something wrong.
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Jarkko Sakkinen

Edited 1 year ago

If I had to guess it is #CSR configuration in a way or another (equivalent to #MSR’s in #x86). You actually learn #CPU architectures only through painful experiences like this, at least according to my past experience :-) Fingers crossed…

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