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Edited 7 months ago
Hmm, I'm having difficulty understanding how interrupts from PCIe devices (with MSI-X support) can be distributed to different processors.

Only an address (to an Local APIC) can be assigned to an interrupt vector?
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@hyeyoo the MSI address and data field encode the destination APIC. See the Intel 64 and IA-32 Architectures Software Developer's Manual chapter 10.11 Message Signalled Interrupts for details.

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@pascaldragon

Oh, in logical mode destination APIC can be encoded as indicating a set of processors instead of a processor.

Thanks!!
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