Conversation
Jon Masters
jonmasters@jonmasters.social
Alastair captures one of the biggest problems with the current RISC-V spec. When I looked into this a while back I was (almost) shocked at the lack of rigor and state of the tooling. I say almost because I expected it, but was still sad. Read his blog.
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Jarkko Sakkinen
jarkko
@jonmasters Even some pretty basic things that would be essential to make meaningful operating system kernels are left out unspecified like decent caching mode configuration (like x86 PAT/MTRR scheme).
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@jonmasters IMHO better way to define multiple things would be think there main applications:
- With MMU spec.
- Without MMU-spec for microcontroller type of stuff.
- Co-processor spec for things like GPU cores (not sure how much this would differ from MMUless tho).
Now it sort of "split by IP block" almost or something like that which is not a good basis for implementing software stack. Probably my split is not exactly correct but the idea is that splits should happen per key applications.
- With MMU spec.
- Without MMU-spec for microcontroller type of stuff.
- Co-processor spec for things like GPU cores (not sure how much this would differ from MMUless tho).
Now it sort of "split by IP block" almost or something like that which is not a good basis for implementing software stack. Probably my split is not exactly correct but the idea is that splits should happen per key applications.
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