Conversation
ppisa

Pavel Pisa

Edited 14 days ago
New release of #qtrvsim #riscv simulator for education. QtRvSim v0.9.8 adds Jiri Stefan's work on branch predictor. Its visualization extends cache, pipeline, memory and other visualization capabilities (https://github.com/cvut/qtrvsim/releases). Online version available at https://comparch.edu.cvut.cz/ . There is new WebEvaluator site link and description available (work of Jakub Pelc) for training on simple assembly and C tasks. The project will be discussed at RISC-V International Special Interest Group: Academia and Training meeting at October 10 2024 at 8 AM Pacific Time (5 PM CEST). The feedback is welcomed. I will be present on 2024 RISC-V Summit North America too.
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ppisa

Pavel Pisa

Reply to @ppisa
I will be happy to see you at RISC-V Summit North America and discuss teaching, Linux, RTEMS, NuttX real time topics and development, motion control and robotics.
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ppisa

Pavel Pisa

Reply to @ppisa
Edited 14 days ago
Damir Gruncl has designed (as part of his thesis - see OTREE thesis list https://gitlab.fel.cvut.cz/otrees/org/-/wikis/theses-defend) RISC-V processor (RVapo) which corresponds to QtRvSim. Sources https://gitlab.fel.cvut.cz/otrees/fpga/rvapo-vhdl . Can be simulated by GHDL, and it is used on Xilinx Zynq as coprocessor for inverse and forward Clarke and Park transformations for PWM cycle by cycle (20 kHz) PMSM motor control (project
https://gitlab.fel.cvut.cz/otrees/fpga/rvapo-apps/-/tree/master/apps/rvapo-pmsm)
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ppisa

Pavel Pisa

Reply to @ppisa
Edited 14 days ago
Our #qtmips simulator has received some minor care as well. Actual release includes Jakub Dupak's memory simulation rework (initially part of RISC-V switch preparation) which allows to run both little and big-endian ELF files. Integrated editor and assembler targets big-endian target only (there is no switch for interactive endianness choice). See https://github.com/cvut/QtMips/releases
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