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ppisa

Pavel Pisa

Edited 26 days ago

The new book how to build #riscv processor for #comparch courses is on the horizon (ETA later H2 2025) RISC-V System-on-Chip Design by D. Harris, J. Stine, R. Thompson, S. Harris. It has been presented at the RISC-V International Academic and Training SIG meeting. The recording of the session is available on YouTube https://youtu.be/Qyq5nHUDt4g The related configurable RV32I to RV64IMAFDCB core and Wally SoC sources https://github.com/openhwgroup/cvw

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