Conversation
ppisa@vhsky.cz

Pavel Pisa

Edited 3 days ago
Pavel Píša: Advanced Computer Architectures – 08 Memory Consistency [M35PAP Winter 25/26]
Show content

Lecture 08 – Multiprocessor Systems and Memory Consistency Problems (PDF)

The Advanced Computer Architectures course main page is https://cw.fel.cvut.cz/wiki/courses/b4m35pap/start

The guidepost to more Czech Technical University in Prague computer architecture teaching materials is provided at https://comparch.edu.cvut.cz/.

There are even Czech language recordings of this course from the Winter Semester 21/22.

Our broader topic knowledge base at https://gitlab.fel.cvut.cz/otrees/org/-/wikis/knowbase.

4
3
0
ppisa

Pavel Pisa

Reply to @ppisa@vhsky.cz

A link to the article about mentioned problem with atomic operations Linux 6.18 Merges Fix For “Catastrophic Performance Issue” On 64-bit ARM at Phoronix.com

0
0
0
ppisa

Pavel Pisa

Reply to @ppisa@vhsky.cz
Edited 3 days ago

Much more precise and detailed texts (papers and books) about scalability including memory ordering by @paulmckrcu are linked from his page http://www2.rdrop.com/users/paulmck/. The detailed Summary of Memory Ordering choices for current CPU architectures is documented in the Table 15.5 Chapter 15. Advanced Synchronization: Memory Ordering of his book Is Parallel Programming Hard, And If So, What Can You Do About It?.

0
0
1
ppisa@vhsky.cz

Pavel Pisa

Reply to @ppisa@vhsky.cz
Edited 3 days ago
The current cmpxchg x86 implementation in the Linux kernel 6.18 at line [109 of arch/x86/include/asm/cmpxchg.h](https://elixir.bootlin.com/linux/v6.18/source/arch/x86/include/asm/cmpxchg.h#L109). The [6.11.2 Extended Asm - Assembler Instructions with C Expression Operands](https://gcc.gnu.org/onlinedocs/gcc-15.2.0/gcc/Extended-Asm.html) of GCC Manual describes constrains and mechanism of binding C code variables to assembly fragments.The RISC-V version implemented by Atomic extension at lne [179 of file arch/riscv/include/asm/cmpxchg.h](https://elixir.bootlin.com/linux/v6.18/source/arch/riscv/include/asm/cmpxchg.h#L179) and implementation using Load Reserve and Store Conditional [Listing 2 - Sample code for compare-and-swap function using LR/SC.](https://docs.riscv.org/reference/isa/unpriv/a-st-ext.html#cas) in the chapter ["A" Extension for Atomic Instructions, Version 2.1](https://docs.riscv.org/reference/isa/unpriv/a-st-ext.html).
0
0
0
ppisa

Pavel Pisa

Reply to @ppisa@vhsky.cz

Links to related Ticket Lock code example for individual architectures:

Kernel Spinlock documentation at LWN.net from test-and-set over ticket-spinlocks to scalable MCS locks and qspinlocks.

0
0
0
About social.kernel.org

Terms of service

  1. Please do not use this service in violation of the Linux Kernel Code of Conduct. Doing so will result in your account suspension with the referral of the matter to the CoC committee.

  2. "Repeating"/"boosting" someone else's status on this platform will be treated as endorsement and will fall under rule #1.

  3. You are encouraged to use this platform to promote your work on the Linux Kernel, but there is no restriction on permitted topics (with the exception of anything covered by #1 above).

  4. There is no requirement to post in English, but it should be considered the primary language of communication on this platform.

Privacy notice

The admins of this service have access to all posted statuses. They aren't looking, but if it's something they shouldn't know about, then you should not post it on this platform.

Please see the Linux Foundation Privacy Policy, which applies to this platform as well.

Getting your own account

If you would like an account on this instance, please check that the following applies to you:

  • You are listed in MAINTAINERS or CREDITS

  • OR: You have a kernel.org account or email address

  • OR: You have a long and established history of involvement with the Linux Kernel

If the above is true and you agree with the Terms of Service and Privacy Notice listed above, please use these instructions to request an account: