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ppisa@vhsky.cz

Pavel Pisa

Edited 22 days ago
Pavel Píša: Advanced Computer Architectures – 13 – ARM and RISC-V [M35PAP Winter 25/26]
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Lecture 13 - 2 – Time and space parallelization in practice – ARM, AArch64, RISC-V (PDF)

The Advanced Computer Architectures course main page is https://cw.fel.cvut.cz/wiki/courses/b4m35pap/start

The guidepost to more Czech Technical University in Prague computer architecture teaching materials is provided at https://comparch.edu.cvut.cz/.

There are even Czech language recordings of this course from the Winter Semester 21/22.

Our broader topic knowledge base at https://gitlab.fel.cvut.cz/otrees/org/-/wikis/knowbase.

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ppisa

Pavel Pisa

Reply to @ppisa@vhsky.cz
Mistake in description on the slide 11: Apple M1 Firestorm core maximal load-store throughput is 3× LD + 1× ST in parallel or 2× LD + 2× ST in parallel. I have tried to keep pace and said incorrect numbers.
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ppisa

Pavel Pisa

Reply to @ppisa@vhsky.cz
Edited 22 days ago

#RISCV The presentation slides on the RISC-V architecture have been extended for later readers, with a more detailed list of basic and RVA23-related extensions to cover topics discussed with students during lecture. See PDF. The link to the Linux kernel device tree for the discussed OrangePi.

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ppisa

Pavel Pisa

Reply to @ppisa@vhsky.cz
Edited 15 days ago

If you have interest in basic or more advanced computer architectures learning and teaching then I plan to visit #RISCV #FOSDEM devroom this Satturday. We can discuss even use of our #QtRvSim in the teaching. We are working on Sv32 and latter even Sv39 addition to extend this tool even for teaching operating system basic concepts. Tenative goal is to run MIT-PDOS one day. We have new #QtRvSim manual at our #CompArch site as well and revamped online training site (thanks to Jakub Pelc https://swpelc.eu/).

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