Jarkko Sakkinen
jarkko
I've mostly used #Lauterbach probes in the past but not very often.
So anyway, I grabbed the info from Internet that with #VisionFive2 SBC Segger J-link family of probes are known to work. Are they my only choice or is there some good and perhaps cheaper but compatible options?
#riscv
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@jarkko My guess would be something like https://www.olimex.com/Products/ARM/JTAG/ARM-USB-TINY-H/ and OpenOCD.
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I'm familiar with OpenOCD. I use it at the university for prototype SoC (https://sochub.fi/). I plan to develop exactly scripts for it that I can develop and test with my SBC and then tune them to work with the SoC once I get them working on off-the-shelf hardware...
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@jarkko Low-level JTAG is an IEEE standard. The RISC-V specifics of how the IR/DR resources work are in this part of the debug spec. https://github.com/riscv/riscv-debug-spec/blob/main/dtm.adoc
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@Fishwaldo @jarkko From https://wiki.sipeed.com/hardware/en/logic_analyzer/combo8/use_cklink_function.html it looks like CKLINK is at least a custom header, with a combo of UART and JTAG. You'll have to look into which header works with what board, and then whether the chip partially or wholely supports RISC-V debug directly via the JTAG interface.
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@Fishwaldo @jarkko Wow. Perverse incentives.
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Jarkko Sakkinen
jarkko
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From that same article I found the U-boot source for JTAG init: https://github.com/starfive-tech/u-boot/blob/ac0ac696256abf412826d74ee918dd417e207d7b/board/starfive/visionfive2/starfive_visionfive2.c#L354
Can one derive from that init code what kind of probe's are compatible?
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@jarkko @sdbbp it’s proprietary debug protocol for t-head riscv based cores. Eg the TH1520 in the lichee 4a or sophgo based chips.
It operates very similar from a software developers perspective to JTAG but its implementation is slightly different. eg, it doesn’t use openOCD to connect to GDB, but something called THeadDebugServer.
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