Conversation
Jarkko Sakkinen
jarkko
Edited 1 year ago
Some learnings of RISC-V, at least from CVA6 perspective:
- If there is any SATP or PTE sync issue, sprinkle first
sfence.vmatogether withfence.i. It is not optimal but usually ensures stability. Once things are functionally together sync points can be reduced. - Might be CVA6 specific issue but I’ve sometimes had issues with
WPTE’s created without having alsoD, causing odd crashes. So again, I’ve taken the habit of first binding these together and later on reduce.
I’ve yet use ASIC boards, have only used FPGA so far and development versions of CPU’s. I guess these sort of fail-safe practices are more important in early development
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I like in RISC-V that it is pretty fast to build kernel alike environments for S-mode because it has the cleanest state transformations I've seen so far in any CPU, It is a "unikernel first" CPU architecture. And different subsets of the specification scale from CPU cores to application cores, such as GPU cores as demonstrated recently: https://www.tomshardware.com/pc-components/cpus/imagination-and-ventana-to-build-a-risc-v-cpu-gpu-platform
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@hasheddan The only thing I've read with thought is your "RISC-V Bytes" series. Salute and huge appreciation for writing those! Sound stuff.
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Daniel Mangum
hasheddan@types.pl@jarkko appreciate the kind words! Hoping to continue the series, feel free to reach out if you have any suggestions for topics I haven’t covered!
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