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ppisa@vhsky.cz

Pavel Pisa

Edited 3 days ago
Pavel Píša: Advanced Computer Architectures – 08 Memory Consistency [M35PAP Winter 25/26]
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Lecture 08 – Multiprocessor Systems and Memory Consistency Problems (PDF)

The Advanced Computer Architectures course main page is https://cw.fel.cvut.cz/wiki/courses/b4m35pap/start

The guidepost to more Czech Technical University in Prague computer architecture teaching materials is provided at https://comparch.edu.cvut.cz/.

There are even Czech language recordings of this course from the Winter Semester 21/22.

Our broader topic knowledge base at https://gitlab.fel.cvut.cz/otrees/org/-/wikis/knowbase.

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ppisa

Pavel Pisa

Reply to @ppisa@vhsky.cz
Edited 3 days ago

Much more precise and detailed texts (papers and books) about scalability including memory ordering by @paulmckrcu are linked from his page http://www2.rdrop.com/users/paulmck/. The detailed Summary of Memory Ordering choices for current CPU architectures is documented in the Table 15.5 Chapter 15. Advanced Synchronization: Memory Ordering of his book Is Parallel Programming Hard, And If So, What Can You Do About It?.

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ppisa@vhsky.cz

Pavel Pisa

Reply to @ppisa@vhsky.cz
Edited 3 days ago
The current cmpxchg x86 implementation in the Linux kernel 6.18 at line [109 of arch/x86/include/asm/cmpxchg.h](https://elixir.bootlin.com/linux/v6.18/source/arch/x86/include/asm/cmpxchg.h#L109). The [6.11.2 Extended Asm - Assembler Instructions with C Expression Operands](https://gcc.gnu.org/onlinedocs/gcc-15.2.0/gcc/Extended-Asm.html) of GCC Manual describes constrains and mechanism of binding C code variables to assembly fragments.The RISC-V version implemented by Atomic extension at lne [179 of file arch/riscv/include/asm/cmpxchg.h](https://elixir.bootlin.com/linux/v6.18/source/arch/riscv/include/asm/cmpxchg.h#L179) and implementation using Load Reserve and Store Conditional [Listing 2 - Sample code for compare-and-swap function using LR/SC.](https://docs.riscv.org/reference/isa/unpriv/a-st-ext.html#cas) in the chapter ["A" Extension for Atomic Instructions, Version 2.1](https://docs.riscv.org/reference/isa/unpriv/a-st-ext.html).
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ppisa

Pavel Pisa

Reply to @ppisa@vhsky.cz

Links to related Ticket Lock code example for individual architectures:

Kernel Spinlock documentation at LWN.net from test-and-set over ticket-spinlocks to scalable MCS locks and qspinlocks.

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