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Probably some RISC-V stuff, but hopefully other things too ;)
palmer

Palmer Dabbelt

Reply to
@tommythorn I haven't seen the v2, but every other SiFive-based chip has errata and given that the v1 was the most broken of the bunch I'm not super excited on that front.

IMO there's really no way around this: all hardware is a mess, it's just a matter of figuring out how to make it work.
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palmer

Palmer Dabbelt

Reply to
@tommythorn Yep, that's how RISC-V works. This is the same as the T-Head stuff, the ISA folks were very clear that vendors self-certify their implementations. None of those words in the PDF matter.
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palmer

Palmer Dabbelt

Reply to
@baylibre thanks, I couldn’t find the link ;)
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palmer

Palmer Dabbelt

We've got our first user-visible errata that actually breaks something: https://lore.kernel.org/all/CA+V-a8vT3AjnU1-s0k7ff0Y7WLofpHYnJPF+mKVnUspsrPvQtw@mail.gmail.com/
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palmer

Palmer Dabbelt

I was talking to @conor and he's never had a bad DIMM. I'd bet more than half of my DIMM packs have had at least some errors. Not sure if my luck is good in his is bad...
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palmer
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conor

Conor Dooley

Anything riscv spec related melts my brain. The lack of consistent wording between documents, unclear "should"/"must" usage and apparent incompleteness really triggers me. Dunno why, but the (perceived?) lack of clarity in what's mean to be spec documents is highly confusing to me. What seems like a web of interrelated GitHub repos and organisations really doesn't help me either.
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palmer

Palmer Dabbelt

Has anyone submitted to the RISC-V room at FOSDEM yet? As usual I can't tell if Pentabarf is broken or if I'm doing something wrong...
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palmer

Palmer Dabbelt

Reply to @monsieuricon
@monsieuricon I think that's the only time I've ever heard someone say that... ;)
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palmer

Palmer Dabbelt

Reply to @palmer
and @monsieuricon has already pointed me to the docs :) https://korg.docs.kernel.org/social.html
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palmer

Palmer Dabbelt

I don't know how to use this yet.
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