Palmer Dabbelt
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Palmer Dabbelt
palmer
Matt's going to be buying snacks and beer and such for the SF Bay Area RISC-V Meetup soon, so please RSVP if you're planning on coming and haven't yet.
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Palmer Dabbelt
palmer
It took me about 12 hours to notice there was a sock in the sleeve of my jacket, and now I'm really starting to worry about all these patches...
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@cr1901 @brouhaha There's been a bunch of posts, I think I had it at some point but couldn't find it a few weeks ago when I looked. IIRC it's just ldconfig from some distro, maybe Debian? Prabhakar went through a pretty long public debugging process on this one, he's usually in #riscv on libera (not sure if he's around here somewhere).
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@tommythorn Yep, I agree with you again here. That was the argument against allowing T-Head to call their page table attribute stuff compatible with the ISA, it didn't work then and I don't see why it'd work now.
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@tommythorn that's what I'd hope too, but the RISC-V folks have been pretty adamant that it's up to vendors to decide on this one. The general idea was vendors would never ship broken hardware because that would be embarrassing for them, but it's not like that's ever worked before.
IMO we're way better off taking support for the craziness than telling them to fork the software stack. Everything we have is for embedded land right now, so if we push back upstream then vendors will likely just ignore us and ship whatever workarounds they need in their SDKs. Then we'll just have a bunch of incompatible RISC-V-like ports floating around, which would be a huge mess.
IMO we're way better off taking support for the craziness than telling them to fork the software stack. Everything we have is for embedded land right now, so if we push back upstream then vendors will likely just ignore us and ship whatever workarounds they need in their SDKs. Then we'll just have a bunch of incompatible RISC-V-like ports floating around, which would be a huge mess.
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@tommythorn I haven't seen the v2, but every other SiFive-based chip has errata and given that the v1 was the most broken of the bunch I'm not super excited on that front.
IMO there's really no way around this: all hardware is a mess, it's just a matter of figuring out how to make it work.
IMO there's really no way around this: all hardware is a mess, it's just a matter of figuring out how to make it work.
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@tommythorn Yep, that's how RISC-V works. This is the same as the T-Head stuff, the ISA folks were very clear that vendors self-certify their implementations. None of those words in the PDF matter.
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Palmer Dabbelt
palmer
We've got our first user-visible errata that actually breaks something: https://lore.kernel.org/all/CA+V-a8vT3AjnU1-s0k7ff0Y7WLofpHYnJPF+mKVnUspsrPvQtw@mail.gmail.com/
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Palmer Dabbelt
repeated
repeated
Conor Dooley
conor
Anything riscv spec related melts my brain. The lack of consistent wording between documents, unclear "should"/"must" usage and apparent incompleteness really triggers me. Dunno why, but the (perceived?) lack of clarity in what's mean to be spec documents is highly confusing to me. What seems like a web of interrelated GitHub repos and organisations really doesn't help me either.
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Palmer Dabbelt
palmer
Has anyone submitted to the RISC-V room at FOSDEM yet? As usual I can't tell if Pentabarf is broken or if I'm doing something wrong...
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Palmer Dabbelt
palmer
@monsieuricon I think that's the only time I've ever heard someone say that... ;)
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and @monsieuricon has already pointed me to the docs :) https://korg.docs.kernel.org/social.html
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