I guess they finally found a monetization scheme?

I'm kind of tempted to just call it a V70 aero...

With v6.2 being released the other day, I did a bit of a recap to remind myself of what actually
landed this time around for RISC-V. Figured I may as well share it /shrug

With the V2 on the horizon, Cristian Ciocaltea added the VisionFive v1 DT, which has been a long
time coming! Unfortunately, that platform is still not really supported in mainline and may never
get there given it's reliance on non-coherent DMA that is yet to be supported.
He did post some of the out of tree non-coherent dma patches on the list the other day though, and
while that's unlikely to land anytime soon, I hope it gets there eventually :)

Renesas finally joined the RISC-V party for v6.2, with Geert's PR adding the base DT for the
RZ/Five. This platform *also* relies on non-coherent DMA to be fully supported, but that is
currently a work in progress! That work was done by Lab Prabhakar from Renesas.


Palmer's PR is where the actually interesting stuff happens though...
Binglei Wang added support for rethooks, after a rough start with mailer issues!
Drew Jones, while not reviewing, worked on some nice cleanups to alternatives and extension
handling.
Anup got one of his many new-feature support series over the line for PMEM support.
The T-Head c9xx series cores got support for their non-standard PMU variant upstream thanks to
Heiko who has been somewhat of a champion for that platform.
RV32, not to be left out, landed support for dynamic ftrace. That work was carried out by Jamie
Iles, who, as the 32-bit bpf maintainer, clearly has an interest in that part of the arch.
Support for zstd compressed images gained support also, thanks to the work of Jisheng Zhang.
Tong Tiangen extended support for hugepages, Xianting Tian got the remainder of their
VMCOREINFO series over the line & Lui Shixin got HUGE\_VMA{P,LLOC} support enabled.
Jinyu Tang brought in support for updating the tlb & Hal Feng put the finishing touch on the base
support for the VisionFive v1 by added the serial driver for it.
Notable also is a patch from Cleo John, tidying up some styling, as it was their first :)

A whole bunch of others contributed various bits of cleanup and fixes that landed in the v6.2, PR
and for more on those check out the changelog in Palmer's PR:
https://lore.kernel.org/linux-riscv/mhng-f76eb33c-7cc1-426f-8f29-37f6bb78baec@palmer-ri-x1c9/

There were also 4 fixes PRs sent out over the course of the merge window, however none of these
really contained anything particularly significant. A lot of attention recently has been centred
around text patching, so it is no surprise that a number of the fixes are there too, with, out of
the 16 total patches in -fixes, 5 were in this area. Other than that, we had a good few general
correctness bits, for sparse warnings etc

CNX's review of the Vision Five 2: https://www.cnx-software.com/2023/02/12/starfive-visionfive-2-sbc-review-debian-12/

After spending the morning trying to figure out how this Documentation patch could possibly cause boot hangs, it turns out I'm just out of disk space...

This phone autocompletes riscv to roadblock

GUIX on RISC-V bootstrap

QtRvSim talk at FOSDEM

First FOSDEM talk in the RISC-V devroom, on self-hosted systems!

101 strikes again

Are you someone who has a simple fix for something in the Linux kernel, but haven't bothered submitting a patch because you find the email workflow daunting? Can be a bugfix, spelling correction, anything at all.

If so, I want to talk to you! I have tools that simplify this process quite a bit, but I need more feedback from people who aren't long-term Linux maintainers.

Please reach out, either via here or by emailing mricon@kernel.org.

I never thought I’d pay more than the face value for a coin, but I couldn’t believe this was real without seeing one in person.

I was hoping to post this when we had had next year's venue locked down, but we are still not there yet. Anyway, Thanks for all the krill! https://lpc.events/blog/2022/index.php/2022/12/03/thats-a-wrap-thanks-everyone-for-linux-plumbers-2022/

Matt's going to be buying snacks and beer and such for the SF Bay Area RISC-V Meetup soon, so please RSVP if you're planning on coming and haven't yet.

It took me about 12 hours to notice there was a sock in the sleeve of my jacket, and now I'm really starting to worry about all these patches...

@pdp7 has a list of kernel folks <https://github.com/pdp7/mastodon-lists>, you can import it the settings (the import/export tab).

We've got our first user-visible errata that actually breaks something: https://lore.kernel.org/all/CA+V-a8vT3AjnU1-s0k7ff0Y7WLofpHYnJPF+mKVnUspsrPvQtw@mail.gmail.com/

I was talking to @conor and he's never had a bad DIMM. I'd bet more than half of my DIMM packs have had at least some errors. Not sure if my luck is good in his is bad...

Anything riscv spec related melts my brain. The lack of consistent wording between documents, unclear "should"/"must" usage and apparent incompleteness really triggers me. Dunno why, but the (perceived?) lack of clarity in what's mean to be spec documents is highly confusing to me. What seems like a web of interrelated GitHub repos and organisations really doesn't help me either.