Conversation
hyeyoo

Hyeonggon Yoo

Edited 1 year ago
started wondering where it's documented that x86 processors deal with the synonym problem, as they use VIPT data caches.

on ARMv8 processors there is an architectural guarantee that data caches acts as PIPT cache even if it's actually VIPT, so it's guaranteed not to suffer from D-cache aliasing.

I've been heard that there is a similar guarantee on x86 processors but haven't found any official references about it - errr, I guess it's time to read some part of the intel manual.

btw this is quite old but is very nice introduction:
https://www.linuxjournal.com/article/7105
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vbabka

Reply to @hyeyoo
@hyeyoo do x86 really use VIPT? IIRC I've seen that mentioned only for L1, but that always had size/associativity = 4096 so that's kinda moot ;) L2+ were PIPT. Anything changed recently?
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hyeyoo

Hyeonggon Yoo

Reply to @vbabka
@vbabka

Designing VIPT caches where size/associativity <= PAGE_SIZE is a way to avoid the synonym problem, no?

It gets tricky when size/associativity > PAGE_SIZE and it seems both Intel and ARM have patents to deal with it

https://patents.google.com/patent/US11314647B2/en
https://patents.google.com/patent/US20070033318A1/en
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vbabka

Reply to @hyeyoo
@hyeyoo yeah like I've said I've only seen in avoided this way so far, dunno other approaches but presumably they are more complex.
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