TIL:

DMA in PCI(e) means a device initiates memory read/write transactions.

But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)

Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)

@hyeyoo Actually, I don't like the term Direct Memory Acess. IMO Bus Mastering is a better term, because it describes what happens: The device becomes a bus master for the transfer.

@ptesarik Yeah it's quite confusing, at first attempt I searched with the keyword "DMA" and "Direct Memory Access" but couldn't find anything useful - because it's very natural for device to access memory (by becoming bus master)

@hyeyoo @ptesarik nothing useful? You should have found this at least! https://youtu.be/aHREYASypPg?si=ina5Ioagx4_PA-6x

@hyeyoo that is probably because @ptesarik is old enough to still have a post-traumatic response to the "DMA" on an IBM PC, where the "DMA" was not only not a bus mastering thing, but involved a different protocol to access the device memory than the CPU would (and had all sorts odd limitations, because the DMA controller was intended for an older generation of processors). Its speed also didn't increase with the speed of newer processors, so on later generation PCs the DMA transfers (essentially only used on floppies and pre-IDE hard drives) were slower than memory access.

As usual @vbabka didn't get the memo, and followed up with a reference to one DMA channel being used for the DRAM refresh. This was only essentially true for the oldest generations PC, PC/XT machines, but as newer machines (now with dedicated DRAM controllers) strived to be "PC compatible", nobody even dared to use channel 0 for anything else.

:(

@hyeyoo @ptesarik @vbabka you know the machine had a 20-bit physical address space, but the DMA controller only had a 16-bit address counter. So they slapped a latch next to it where you could put the top bits. But the DMA controller was of course blissfully unaware, so even thought you could do transfers from/to anywhere in the 1M of memory, you could never cross a 64K boundary because the top bit wouldn't carry to the latch and the transfer would would roll over back to a 64K boundary instead.

:(((

@hyeyoo @ptesarik @vbabka Intel, of course, wanted to sell more silicon (and get rid of all the stinking software) so they got a chip we'd call a bus mastering DMA engine nowadays -- the 8089.

It was supremely overengineered, programable, and nobody ever used it.

:((

@lkundrak @hyeyoo @ptesarik hehe I was hoping to link the full album, but I suck at youtubing apparently.

@lkundrak @ptesarik @vbabka

heh, the music is much more niche than I thought 😲

@hyeyoo @ptesarik they do live shows tho, but afaik that's a little more metal, with guitars, not just chiptunes and synths. i think @vbabka is attending a show soon

@lkundrak @hyeyoo @ptesarik next Friday!

@lkundrak @hyeyoo @vbabka No, this was good, because this behavior was documented (unlike some other quirks). I wrote a custom SoundBlaster driver which allocated a 64K buffer at a 64K address boundary and then took advantage of rolling over the DMA address if that was the most efficient way to use the buffer.