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looks like there are a bunch of loongarch machines on aliexpress now, interesting

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@ariadne @dr2chase do any of them separate firmware storage from OS filesystems in a meaningful way? Or are they all just emmc hand-off daisy chains?

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@ariadne @dr2chase Was: Re: risc-vwloongarch copying armwrisc-v's biggest mistakes.

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@ariadne @dr2chase okay I don't know how this formatting could be expected of the text form of the tty form of C-w.

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@vathpela @dr2chase the boards i found seem to have dedicated SPI flash for a UEFI boot environment

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@ariadne @dr2chase that is very uncommon for EFI SBCs. And for Jetsons.

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@ariadne @dr2chase outside of Apple those are few and far between. (Inside of Apple it's too dark to read?)

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@ariadne @dr2chase but I'm not sure that exists. Closest I know are Ampere, and they aren't. What system?

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@vathpela @dr2chase i meant for loongarch, the boards are literally ATX PC-class boards

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@ariadne @dr2chase oh, my bad. I have only academic experience, ignore me.

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@ariadne @dr2chase that is interesting, though. It's a case of riscv not just copying arm's mistakes, which is nice.

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@vathpela @ariadne @dr2chase RISC-V with MMU is somewhat unfinished experiment. Hard to even say what it is really, given huge holes in the spec's and a few by definition ambiguous opcodes. Mostly RISC-V in reality is what SiFive implements :-)

I sometimes wonder why people don't just take OpenMIPS, which is almost like finished RISC-V with MMU...
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@vathpela @ariadne @dr2chase And RISC-V specs are as thin as they are as they are lacking proper semantics definitions, e.g. in pseudo code.
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@vathpela @dr2chase @ariadne Yep, in the end of 2021 but how does that connect to RISC-V? :-) My experiences with RISC-V connect to this project: https://sochub.fi/. I've been on industry "sabbatical" for over a year (returning back to some yet-to-be defined company next Oct).
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Jarkko Sakkinen

Edited 1 year ago
Sorry do not connect Intel, Loonghorn and RISC_V to the same sentence ;-)

There's also Russian Elbrus line of CPU's but not Elbrus sold at Ali Express (unfortunately). I might have even bought one if they had that for plain interest... Loongson products I can find easily.
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First could not find them because I was searching for https://longhorn.ms/
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@vathpela @dr2chase @ariadne Do you mean Intel SDM and it is verbose pseudo code by this. If that was the connection, yep, I do appreciate that side in x86 specs :-) I can more easily grasp stuff from SDM than from RISC-V specs.
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@jarkko @vathpela @ariadne I'm a little puzzled how this turned to RISC-V. Loongarch64 is MIPS64 with Chinese characteristics.

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@jarkko @vathpela @ariadne PS your "for more information" link at gitlab.io doesn't seem to have much information, if that is intended to help w/ next-job-obtaining.

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Jarkko Sakkinen

Edited 1 year ago
@vbabka @ariadne @dr2chase @vathpela Yeah one of the most common root design failures when it comes to various side-channel attacks :-) Vulnerability by design. Other would be CPU caches or combination of these two :-)
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@dr2chase @vathpela @ariadne Thanks, should actually make that home page ;-) I've had a few interviews and should update that during July. It is a bit early to close a job contract for most companies at this point.
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@dr2chase @vathpela @ariadne I've been following for the sake of general interest a lot Loonghorn, Elbrus and OpenMIPS, and I spotted riscv keywords in the thread ;-) I've been in a industry sabbatical working on research RISC-V chips: https://www.sochub.fi/. Apologies if I took this off-topic... No bad intentions from my side. CPU's just generally interest me.

Pro tip for the next time: scope exactly which CPU's are allowed, and which are banned in your social media post. If there is official disclaimer that bans this or any other topics. I will promise to follow it! In the top-post there was no such disclaimer, which meant that I was allowed to discuss also other CPU architectures than the aforementioned Loongson :-)
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@vbabka @ariadne @dr2chase @vathpela I actually like a lot the RISC-V version without MMU. It has memory protection based on partitions, which is super secure way to do it (so called PMP registers).
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@dr2chase @ariadne @vathpela Right it has "for more information". Yeah, the current Pelican template probably won't help a lot, agreed
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@dr2chase @ariadne @vathpela I fixed the issue just for you ;-) https://jarkkojs.gitlab.io/

Will add resume PDF made with awesome https://typst.app/ at some point and then I consider it done.
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