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Linux kernel hacker and maintainer etc.

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jarkko

Jarkko Sakkinen

all sort of glitch with #rustlang community comes to personally in the end how you look at a programming language: a language or purely just an opcode generator. one example of such glitch is IMHO unrobust handling of OOM conditions. So you end up getting safe but and super fat and resource wasteful user space programs. But still memory-safe in the language level, which does not provide safety for e.g. any possible DoS attack.
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jarkko

Jarkko Sakkinen

tonights jam, something in progress #bitwig
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jarkko

Jarkko Sakkinen

Reply to @laund@hachyderm.io
@laund implement even a PoC quality version of SBI on top of Embassy. Then I'm super interested. Even just bare bones baseline for development an something is provably in working condition. There's some dead looking SBI crate but I would see more future in implementing one top of this more or less accepted framework called Embassy I suppose. Not that I'm too familiar with that either. I just hack CPU's, that what I do in the end....
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jarkko

Jarkko Sakkinen

Reply to @laund@hachyderm.io
@laund AFAIK does not provide SBI implementation (could be wrong too) so not really what I was looking after.
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jarkko

Jarkko Sakkinen

Lot's of RISC-V posts but here's one more. I think it has a strong future in post-#quantum world. QPU is like GPU, i.e. it is great for certain types of computations but it sucks for branching binary logic that I/O relies on. In that world correctness of stuff that is done with semiconductors is hugely more important than now and that's where open, modular and within constraints formally verifiable CPU architecture shines.

#riscv
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jarkko

Jarkko Sakkinen

If most of firmware stack in RISC-V was rustified so that you could build compatible SBI implementation with cargo build, that would be the most effective embedded product creation platform that I could think of. You could move from product idea rapidly to a product PoC.

#riscv #rustlang
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jarkko

Jarkko Sakkinen

Reply to @jarkko
@josh If I wanted something like I'd look how BuildRoot thing is implemented, and derive something more generic from that. The reason being that it is already pretty well field tested.
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jarkko

Jarkko Sakkinen

Reply to @jarkko
@josh See sections 8.9-8.11 of https://buildroot.org/downloads/manual/manual.html#_graphing_the_dependencies_between_packages
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jarkko

Jarkko Sakkinen

Reply to @josh@joshtriplett.org
@josh BuildRoot can do graphs. It is based on kbuild so pretty close at least.
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jarkko

Jarkko Sakkinen

I wonder if #BeagleV has similar #DIP switch as #VisionFive2, which works as a selector for different boot modes?

In VisionFive2 you can choose to:

  1. Boot from SPI flash.
  2. Boot from SD (including U-boot and OpenSBI, assumes a particular partition layout).
  3. Rescue UART boot mode.

These VisionFive2 e.g. pretty capable board for prototyping CPU extensions.

#riscv #sbc #uboot #opensbi

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jarkko

Jarkko Sakkinen

Edited 2 years ago
I like how easy it is with RISC-V to emulation ISA extensions by emulating privileged instructions in M-mode. that makes it pretty good production creation platform when you have something in-between FPGA and QEMU. I.e. you can take ASIC board and build a PoC with customized OpenSBI. #riscv #opensbi #fpga #qemu
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jarkko

Jarkko Sakkinen

after years of using #voxengo #span i've started using #tokyodawnlab's new and free #prism: https://www.tokyodawn.net/tdr-prism/
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jarkko

Jarkko Sakkinen

Reply to @tommythorn@chaos.social
@tommythorn yeah, my usage model for SBC"s is such that I most of the time have a new image per boot because I use the image just to test e.g. a code change to kernel or sometimes firmware. like e.g. with this one i have not ever even tried to connect it to a network or display, all comms through TTL-USB. if you test e.g. kernel on many different SBC's, then a workflow is required where you do not need to connect many cables. surviving with just USB power and TTL-USB with the whole range is optimal because all SBC's I know follow the same GPIO layout as RPi.
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jarkko

Jarkko Sakkinen

Reply to @adingbatponder@fosstodon.org
@adingbatponder search for "iu-boot documentation visionfive 2" if there is problem with the link :-) it is just official u-boot dociumentation.
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jarkko

Jarkko Sakkinen

Reply to @tommythorn@chaos.social
@tommythorn Yeah, I have no idea at this point what is the early boot code in this board. Even if you completely brick the SPI flashed firmware you can boot the board in "UART mode" and flash it. So there's something below with quite a bit of functionality.
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jarkko

Jarkko Sakkinen

Reply to @adingbatponder@fosstodon.org
@adingbatponder I just went to U-boot homepage to see what they have on the board. See the link in the previous comment.
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jarkko

Jarkko Sakkinen

Reply to @jarkko
@tommythorn Legit question but yeah for stuff that I'm doing with it being able to supply U-boot and OpenSBI is great.
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jarkko

Jarkko Sakkinen

Reply to @tommythorn@chaos.social
@tommythorn there's first stage loader, which loads either from internal flash or SD card with specific partition structure. I've based my experiments on U-boot documentation: https://docs.u-boot.org/en/latest/board/starfive/visionfive2.html.
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jarkko

Jarkko Sakkinen

Edited 2 years ago
Nice, with the DIP switches Starfive VisionFive 2 SBC can be made to boot the full chain from SD card. Initially booting from SPI flash for any possible use for this never really makes sense. It is a badly chosen default for this sort of maker and/or developer product :-) #riscv #opensbi #uboot #starfive #visionfive2 #keystone
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jarkko

Jarkko Sakkinen

Log grabbing pattern for pretty_env_logger. when tracing #Rust #TUI applications;

RUST_LOG=debug target/debug/tior open /dev/ttyUSB0 2> log.txt

#rustlang

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