I try to learn at least one RISC-V opcode a day to get more familiar. Today’s opcode was auipc which stores to a register a PC-relative address from an immediate offset. The offset is given as number of pages.
It is e.g. used to set the gp (which is mnemonic for x3), which is the base address for global variables.
Not trying to teach anyone. Writing things down like this just works for my memory :-)
Have been passive at #LKML because I’m stuck with this page table sync bug in #Keystone: https://github.com/keystone-enclave/keystone/issues/378.
Snippet where it trips:
sfence.vma
csrw satp, a0 // switch to virtual addresssing
sfence.vma
mtval is at the 2nd sfence.vma when misaligned store happens.
This never happens on QEMU and I presume that not on all hardware but I’ve tested this only with CVA6 (running on Genesys2 FPGA board). On QEMU everything just works.
At least, shouldn’t the sfence.vma be sort “useless” as it should continue where stvec is set, right? I guess here one thing to try out would be to simply remove the second sfence.vma?
I’m really just learning RISC-V sync opcodes and do not know e.g. when I should use also fence.i. Just trying different things without tbh knowing exactly what I’m doing yet…
In head.S there is also .align 2 after csrw and I have to admit that I don’t know exactly why… This bug is haunting me…