Some learnings of RISC-V, at least from CVA6 perspective:
sfence.vma
together with fence.i
. It is not optimal but usually ensures stability. Once things are functionally together sync points can be reduced.W
PTE’s created without having also D
, causing odd crashes. So again, I’ve taken the habit of first binding these together and later on reduce.I’ve yet use ASIC boards, have only used FPGA so far and development versions of CPU’s. I guess these sort of fail-safe practices are more important in early development
75% time went to exclusion, i.e. finding that the bug is in the enclave itself, not in kernel, SDK or the security monitor. Last two weeks was peeking and poking with loader.S
. I even wrote a new driver for Keystone in the process so that I could exclude the driver (OTT driver is, well, I don’t want to say anything impolite…).
I nailed the Keystone SATP change bug on CVA6 after only 1.5 months of constant debugging: