Jarkko Sakkinen
Posts
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478OpenPGP: 3AB05486C7752FE1
heck maybe it would be even possible to fixup "knowingly known cryptographic material" that would be fixed up also to the qemu code base to which Intel's and AMD's servers would respond as legitimately.or maybe salt somehow to stamp the fake stamp. like just for infrasturcuture QA type of stuff use.
this is not an issue in the CA part as e.g. AMD already today has a rate-limited attestation paradigm. so yeah i think really would make sense for companies to spend money for fixing up this.
this is not an issue in the CA part as e.g. AMD already today has a rate-limited attestation paradigm. so yeah i think really would make sense for companies to spend money for fixing up this.
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Jarkko Sakkinen
jarkko
imho at least qemu would need snp and tdx emulation in upstream for like testing patches. i mean most have x86 so even rigged emulation would do the job for trivial patch testing
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So apparently (after searching) there is previous work https://patchwork.kernel.org/project/keyrings/cover/20200518172704.29608-1-prestwoj@gmail.com/. So I guess I just use some of it (and make it a separate patch with appropriate credits).
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Also a bit unclear what is best bet for authentication but it is a non-concern for RFC.
One possible argument for just authentication value at most would be that LUKS2 already blesses with TPM2 policy and kernel communicates by using null seed derived key. Using policy adds robustness but is it worth of added complexity to have two layers of policy, I really don't know at this point.
One possible argument for just authentication value at most would be that LUKS2 already blesses with TPM2 policy and kernel communicates by using null seed derived key. Using policy adds robustness but is it worth of added complexity to have two layers of policy, I really don't know at this point.
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OK, now I have together ASN.1 parsing and new key subtype "tpm2_key_subtype", which is foundations for TPM2 asymmetric keys.
Only compile-tested ;-) This is now bare minimum to trial in QEMU. Lot's of dance relocating necessary bits of trusted keys code to the TPM driver (only ASN.1 parser at this point).
Only compile-tested ;-) This is now bare minimum to trial in QEMU. Lot's of dance relocating necessary bits of trusted keys code to the TPM driver (only ASN.1 parser at this point).
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Jarkko Sakkinen
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Phoronix
phoronix@masto.aiSDL3 Adds PipeWire Camera Support
Adding to the growing list of features coming with the SDL3 release for this hardware/software abstraction layer commonly used by cross-platform games and other software is PipeWire camera capturing support...
https://www.phoronix.com/news/SDL3-PipeWire-Camera-Capture
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Jarkko Sakkinen
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9to5Linux
9to5linux@floss.social
Edited 1 year ago
#GNOME 47 Desktop Environment Is Slated for Release on September 18th, 2024 https://9to5linux.com/gnome-47-desktop-environment-release-date-slated-for-september-18th-2024
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Jarkko Sakkinen
jarkko
#Amaranth sounds like a name of a black/death metal band from Scandinavia but is actually pretty neat hardware (#FPGA) synthesis framework:
https://amaranth-lang.org/docs/amaranth/latest/intro.html
https://amaranth-lang.org/docs/amaranth/latest/intro.html
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Jarkko Sakkinen
jarkko
working on RFC patch for TPM2 asymmetric keys (will use null seed encrypted session) for supporting x509: https://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git/commit/?h=tpm2_key
https://datatracker.ietf.org/doc/draft-woodhouse-cert-best-practice/
https://datatracker.ietf.org/doc/draft-woodhouse-cert-best-practice/
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What is the most difficult task in kernel development? Emails ;-)
That said,it is still the best available in my opinion :-) Email archives are much nicer to backtrack even multiple years behind than these crazy Git issue trackers. I.e. there is a clear timeline in communications.
That said,it is still the best available in my opinion :-) Email archives are much nicer to backtrack even multiple years behind than these crazy Git issue trackers. I.e. there is a clear timeline in communications.
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@jmorris off-topic but i have this sound card called "RME BabyFace Pro FS". it has pretty cool idea for FPGA's: the mixer is an FPGA. With this topology it can reach 1 ms latency for audio. And i.e. a firmware update contains also potentially update for the FPGA. Pretty clever hybrid approach IMHO.
Before I got this sound card I was not really sure where application wise it would make sense to have e.g. a SoC combined with FPGA but this product made me understand it a bit better.
I also own one small lattice FPGA. As soon as I get an idea how to use it e.g. with RPi for similar hybrid thing I'll definitely will PoC something. Lattice's have the benefit of having open source FPGA stack and since I also have a SoC FPGA does not have to have too many logic ports.
Before I got this sound card I was not really sure where application wise it would make sense to have e.g. a SoC combined with FPGA but this product made me understand it a bit better.
I also own one small lattice FPGA. As soon as I get an idea how to use it e.g. with RPi for similar hybrid thing I'll definitely will PoC something. Lattice's have the benefit of having open source FPGA stack and since I also have a SoC FPGA does not have to have too many logic ports.
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@jmorris off-topic but i have this sound card called "RME BabyFace Pro FS". it has pretty cool idea for FPGA's: the mixer is an FPGA. With this topology it can reach 1 ms latency for audio. And i.e. a firmware update contains also potentially update for the FPGA. Pretty clever hybrid approach IMHO.
Before I got this sound card I was not really sure where application wise it would make sense to have e.g. a SoC combined with FPGA but this product made me understand it a bit better.
I also own one small lattice FPGA. As soon as I get an idea how to use it e.g. with RPi for similar hybrid thing I'll definitely will PoC something. Lattice's have the benefit of having open source FPGA stack and since I also have a SoC FPGA does not have to have too many logic ports.
Before I got this sound card I was not really sure where application wise it would make sense to have e.g. a SoC combined with FPGA but this product made me understand it a bit better.
I also own one small lattice FPGA. As soon as I get an idea how to use it e.g. with RPi for similar hybrid thing I'll definitely will PoC something. Lattice's have the benefit of having open source FPGA stack and since I also have a SoC FPGA does not have to have too many logic ports.
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