Hyeonggon Yoo
Posts
469Following
90Followers
94- Intern @ NVIDIA Korea (Security System Software) (2024.06 ~)
- Ex-Intern @ Panmneisa (CXL emulation stuff) (~2023.12)
- Undergraduate majoring CSE (estimated graduation: Feb. 2025)
- Working as reviewer at Linux Slab subsystem
- Born in August 6, 2000
Opinions are my own.
My interests are:
Memory Management,
Computer Architecture,
Circuit Design,
Virtualization
Hyeonggon Yoo
hyeyoo
Edited 1 year ago
Why do we have two different specifications about firmware interface (UEFI and ACPI)?
Why can't UEFI (Unified EFI) unify everything :/
Why can't UEFI (Unified EFI) unify everything :/
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
How do memory controllers "map" device resources (memory or registers) with address spaces assigned via PCI BARs into system memory address space? Is there a FPGA device in it the controller?
This whole question may be wrong as Iack some knowledge about it.
This whole question may be wrong as Iack some knowledge about it.
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Hyeonggon Yoo
hyeyoo
Hmm what's the point of PCIe Root Complex-Integrated Endpoints (RCiEP) rather than Endpoints connected to Root Port
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
In the ACPI specification; the character representing ACPI root namespace ('\') seems to be escaped (' and \') and looks like this.
How have people been reading this?
How have people been reading this?
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
my keyboard is not responding until the kerenel is loaded. what's wrong I want uefi please
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
UEFI (Unified Extensible Firmware Interface) standard defines the interface between platform firmware and OS (loader). UEFI only standards the interface with the firmware, but its implementation follows the Platform Integration (PI) standard, not UEFI. UEFI completely replaces BIOS used in traditional IBM PC environments.
An OS loader reads information such as ACPI tables, memory maps, etc. through UEFI and passes it to OS, which then takes over control. Most of the services provided by UEFI, including the ACPI Table and Memory Map, are not accessible after OS loader calls the UEFI's Boot Service ExitBootServices().
Intel provides open source reference implementations of firmware that adhere to the UEFI standard called EDK 2. The firmware also implements PCI host bus controllers, bus drivers, and device drivers.
In order to add CXL memory to the memory map during system initialization, the firmware must have CXL support added so that you can set up a CXL host bridge, switch, and device at system initialization before OS has taken the control.
An OS loader reads information such as ACPI tables, memory maps, etc. through UEFI and passes it to OS, which then takes over control. Most of the services provided by UEFI, including the ACPI Table and Memory Map, are not accessible after OS loader calls the UEFI's Boot Service ExitBootServices().
Intel provides open source reference implementations of firmware that adhere to the UEFI standard called EDK 2. The firmware also implements PCI host bus controllers, bus drivers, and device drivers.
In order to add CXL memory to the memory map during system initialization, the firmware must have CXL support added so that you can set up a CXL host bridge, switch, and device at system initialization before OS has taken the control.
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
In ACPI-compatible OS environment, NUMA node of memory ranges and distance matrix between NUMA nodes are parsed from ACPI SRAT/SLIT tables and they are provided firmware.
ACPI HMAT describes latency/bandwidth characteristics.
CDAT is a set of registers in CXL that reports bandwidth/latency characteristics of CXL devices/switches. it is consumed by firmware to produce HMAT/SRAT tables.
ACPI HMAT describes latency/bandwidth characteristics.
CDAT is a set of registers in CXL that reports bandwidth/latency characteristics of CXL devices/switches. it is consumed by firmware to produce HMAT/SRAT tables.
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Hyeonggon Yoo
repeated
repeated
AkaSci 🛰️
AkaSci@fosstodon.org
Edited 1 year ago
NASA is sending a software update to the Voyager 2 spacecraft today!
Data will be sent at 16 bps with a 19 kW transmitter using the 70-m dish at DSN Canberra.
Distance: 20 billion km
Light travel time: 18:40 hours
The patch contains logic to recover from glitches similar to the one in May 2022, when the AACS system on Voyager 1 was sending garbled data. The root cause was not diagnosed. The patch will be activated on Oct 28. Voyager 2 will be next.
https://www.jpl.nasa.gov/news/nasas-voyager-team-focuses-on-software-patch-thrusters
#Voyager
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