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A relatively new professional kernel hacker, born in August 6, 2000, and living in Korea (South!).

- Linux Kernel Developer @ Oracle (Linux Kernel MM) (2025.02 ~ Present)
- Reviewer for the Linux Slab subsystem
- Former Intern @ NVIDIA, SK Hynix, Panmnesia (Security, MM and CXL)
- B.Sc. in Computer Science & Engineering, Chungnam National University (Class of 2025)

Opinions are my own.

My interests are:
Memory Management,
Computer Architecture,
Circuit Design,
Virtualization
@bagder wait, do even wearables use curl?
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@lkundrak @ptesarik @vbabka

heh, the music is much more niche than I thought 😲
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Harry (Hyeonggon) Yoo

what, there's a script to import linux kernel headers to QEMU.

From commit 412a8245 ("pci_regs.h: import from linux"):
```
It seems to make sense to import pci_regs.h from linux: why maintain our own?

As a first step, move the header to standard-headers, and add it to the update script.
```
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@vbabka micro-benchmark then
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I'm a little surprised and disappointed that the 2023 Linux Foundation TAB election only has five candidates running for the five open seats. All five of the candidates are existing TAB members.

It would seem like one of the issues the TAB should focus on this year is getting more people interested in TAB participation.

https://lore.kernel.org/lkml/e851a8e5-c4c2-4b5d-887a-509e591cff49@intel.com

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Harry (Hyeonggon) Yoo

Edited 1 year ago
The last one (I think) is having only limited time budget to read.
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Harry (Hyeonggon) Yoo

Edited 1 year ago
Another big hurdle is just reading code without knowing what's behind.
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Harry (Hyeonggon) Yoo

Edited 1 year ago
A big barrier to reading and analyzing code is a psychological resistance to reading unfamiliar text
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Harry (Hyeonggon) Yoo

Edited 1 year ago
@ptesarik Yeah it's quite confusing, at first attempt I searched with the keyword "DMA" and "Direct Memory Access" but couldn't find anything useful - because it's very natural for device to access memory (by becoming bus master)
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Harry (Hyeonggon) Yoo

What kind of benchmark is it
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Harry (Hyeonggon) Yoo

Edited 1 year ago
TIL:

DMA in PCI(e) means a device initiates memory read/write transactions.

But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)

Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)
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Harry (Hyeonggon) Yoo

Edited 1 year ago
It's already 1am but 3 hours left until CXL MC... uh, I'm tired
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@linuxplumbersconf Youtube Live Stream URLs are now available on the Schedule Overview page (https://lpc.events/event/17/timetable/#all).

Find the track you want and click the paperclip on the upper right corner to bring up the Live Stream Link

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@lkundrak @phooky
I think I saw it in the dark corner of my room
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Harry (Hyeonggon) Yoo

Edited 1 year ago
This winter I'm going to do a research project (for the first time in my life!) with other students, at Purdue University (Indiana).

2 months is bit short for a project, so we need to find a very small question that no one has answered.

It seems I've found a question suitable for our need in the compiler area, but I need to consult with the professor to verify if it's a valid question.
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Harry (Hyeonggon) Yoo

Edited 1 year ago
@ljs sir, CXL controller market will be $762.7 million industry in 2029.
wait how does it know if it would survive at all
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Harry (Hyeonggon) Yoo

After 2 months of learning related stuffs I finally feel like I'm ready to dive into CXL device emulation code.
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@ptesarik @ljs @huawei

Oh, it wasn't something I was aware of. thank you for letting me know!

But doesn't it require prior research experience?
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@ljs I don't like nor am good at making a choice tbh
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