Hyeonggon Yoo
Posts
469Following
90Followers
94- Intern @ NVIDIA Korea (Security System Software) (2024.06 ~)
- Ex-Intern @ Panmneisa (CXL emulation stuff) (~2023.12)
- Undergraduate majoring CSE (estimated graduation: Feb. 2025)
- Working as reviewer at Linux Slab subsystem
- Born in August 6, 2000
Opinions are my own.
My interests are:
Memory Management,
Computer Architecture,
Circuit Design,
Virtualization
Hyeonggon Yoo
hyeyoo
Edited 1 year ago
A few diagrams about PCIe. 1) An example PCIe topology 2) PCIe Switch and 3) Root Complex
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Hyeonggon Yoo
hyeyoo
what, there's a script to import linux kernel headers to QEMU.
From commit 412a8245 ("pci_regs.h: import from linux"):
```
It seems to make sense to import pci_regs.h from linux: why maintain our own?
As a first step, move the header to standard-headers, and add it to the update script.
```
From commit 412a8245 ("pci_regs.h: import from linux"):
```
It seems to make sense to import pci_regs.h from linux: why maintain our own?
As a first step, move the header to standard-headers, and add it to the update script.
```
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Hyeonggon Yoo
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Paul Moore
securepaul@fosstodon.orgI'm a little surprised and disappointed that the 2023 Linux Foundation TAB election only has five candidates running for the five open seats. All five of the candidates are existing TAB members.
It would seem like one of the issues the TAB should focus on this year is getting more people interested in TAB participation.
https://lore.kernel.org/lkml/e851a8e5-c4c2-4b5d-887a-509e591cff49@intel.com
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Hyeonggon Yoo
hyeyoo
@alphaville
Alternatively you can pretend to understand the Linux kernel
https://medium.com/@c0ngwang/how-to-pretend-to-be-a-linux-kernel-expert-b1ca21ac6384
Alternatively you can pretend to understand the Linux kernel
https://medium.com/@c0ngwang/how-to-pretend-to-be-a-linux-kernel-expert-b1ca21ac6384
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
A big barrier to reading and analyzing code is a psychological resistance to reading unfamiliar text
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@ptesarik Yeah it's quite confusing, at first attempt I searched with the keyword "DMA" and "Direct Memory Access" but couldn't find anything useful - because it's very natural for device to access memory (by becoming bus master)
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
TIL:
DMA in PCI(e) means a device initiates memory read/write transactions.
But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)
Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)
DMA in PCI(e) means a device initiates memory read/write transactions.
But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)
Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
It's already 1am but 3 hours left until CXL MC... uh, I'm tired
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Hyeonggon Yoo
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James Bottomley
jejb@mastodon.online@linuxplumbersconf Youtube Live Stream URLs are now available on the Schedule Overview page (https://lpc.events/event/17/timetable/#all).
Find the track you want and click the paperclip on the upper right corner to bring up the Live Stream Link
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Hyeonggon Yoo
hyeyoo
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