Some learnings of RISC-V, at least from CVA6 perspective:
sfence.vma together with fence.i. It is not optimal but usually ensures stability. Once things are functionally together sync points can be reduced.W PTEâs created without having also D, causing odd crashes. So again, Iâve taken the habit of first binding these together and later on reduce.Iâve yet use ASIC boards, have only used FPGA so far and development versions of CPUâs. I guess these sort of fail-safe practices are more important in early development