Hyeonggon Yoo
Posts
399Following
84Followers
87- Pre-Intern @ NVIDIA Korea (Security System Software) (2024.06 ~)
- Ex-Intern @ Panmneisa (CXL emulation stuff) (~2023.12)
- Undergraduate majoring CSE (estimated graduation: Feb. 2025)
- Working as reviewer at Linux Slab subsystem
- Born in August 6, 2000
Opinions are my own.
My interests are:
Memory Management,
Computer Architecture,
Circuit Design,
Virtualization
Hyeonggon Yoo
hyeyoo
Edited 9 months ago
TIL:
DMA in PCI(e) means a device initiates memory read/write transactions.
But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)
Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)
DMA in PCI(e) means a device initiates memory read/write transactions.
But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)
Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)
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Hyeonggon Yoo
hyeyoo
Edited 9 months ago
It's already 1am but 3 hours left until CXL MC... uh, I'm tired
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Hyeonggon Yoo
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James Bottomley
jejb@mastodon.online@linuxplumbersconf Youtube Live Stream URLs are now available on the Schedule Overview page (https://lpc.events/event/17/timetable/#all).
Find the track you want and click the paperclip on the upper right corner to bring up the Live Stream Link
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Hyeonggon Yoo
hyeyoo
Edited 10 months ago
This winter I'm going to do a research project (for the first time in my life!) with other students, at Purdue University (Indiana).
2 months is bit short for a project, so we need to find a very small question that no one has answered.
It seems I've found a question suitable for our need in the compiler area, but I need to consult with the professor to verify if it's a valid question.
2 months is bit short for a project, so we need to find a very small question that no one has answered.
It seems I've found a question suitable for our need in the compiler area, but I need to consult with the professor to verify if it's a valid question.
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Hyeonggon Yoo
hyeyoo
After 2 months of learning related stuffs I finally feel like I'm ready to dive into CXL device emulation code.
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Hyeonggon Yoo
hyeyoo
Edited 10 months ago
a foolish mistake: can't open my phone's card wallet because of the strap I bought yesterday...
Should've realized that I can't have both :(
Should've realized that I can't have both :(
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Hyeonggon Yoo
hyeyoo
Edited 10 months ago
There are two ways to access device registers in PCIe:
1) As an extended capability in PCIe extended configuration space, (Designated) Vendor-Specific Extended Capabilities can be used to access vendor-specific registers. As more than one vendor produces CXL devices, DVSEC is used instead of VSEC.
2) BARs can be used to map device resources (registers or memory) into system memory address space.
Errrr.. btw many registers are there in the CXL spec :/
Notably:
- (DVSEC) "PCIe DVSEC for CXL Device" is used to identify CXL-capable PCIe endpoints
- (DVSEC) "Register Locator DVSEC" is used to locate CXL memory-mapped registers
- (Memory-Mapped) "CXL 2.0 Component Registers" is used to configure CXL Components (Host Bridge, Root Port, Upstream/Downstream Port, Device)
- (Memory-Mapped) "CXL Device Register Interface" is used to access CXL device registers and issue commands to a CXL device
Configuration space of Every CXL 2.0 component can be accessed via the standard PCIe method, except Host Bridges. Component Registers of CXL Host Bridges are located by ACPI CEDT table, which also contains CFMWS (CXL Fixed-Memory-Window Structure).
1) As an extended capability in PCIe extended configuration space, (Designated) Vendor-Specific Extended Capabilities can be used to access vendor-specific registers. As more than one vendor produces CXL devices, DVSEC is used instead of VSEC.
2) BARs can be used to map device resources (registers or memory) into system memory address space.
Errrr.. btw many registers are there in the CXL spec :/
Notably:
- (DVSEC) "PCIe DVSEC for CXL Device" is used to identify CXL-capable PCIe endpoints
- (DVSEC) "Register Locator DVSEC" is used to locate CXL memory-mapped registers
- (Memory-Mapped) "CXL 2.0 Component Registers" is used to configure CXL Components (Host Bridge, Root Port, Upstream/Downstream Port, Device)
- (Memory-Mapped) "CXL Device Register Interface" is used to access CXL device registers and issue commands to a CXL device
Configuration space of Every CXL 2.0 component can be accessed via the standard PCIe method, except Host Bridges. Component Registers of CXL Host Bridges are located by ACPI CEDT table, which also contains CFMWS (CXL Fixed-Memory-Window Structure).
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Hyeonggon Yoo
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Kees Cook 
kees@fosstodon.org
Here's how to enable the kernel Memory Tagging Extension (#MTE) on the Pixel 8:
adb shell setprop arm64.memtag.bootctl memtag,memtag-kernel
I'm so happy there's real-world hardware finally available to provide mitigations against linear buffer overflows and many types of use-after-free flaws.
More details here:
https://outflux.net/blog/archives/2023/10/26/enable-mte-on-pixel-8/
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Hyeonggon Yoo
hyeyoo
I have a thing (wanna do at some point in my life) for designing processors, memory modules and neuromorphic processors
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Hyeonggon Yoo
hyeyoo
Edited 10 months ago
Why do we have two different specifications about firmware interface (UEFI and ACPI)?
Why can't UEFI (Unified EFI) unify everything :/
Why can't UEFI (Unified EFI) unify everything :/
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Hyeonggon Yoo
hyeyoo
Edited 10 months ago
How do memory controllers "map" device resources (memory or registers) with address spaces assigned via PCI BARs into system memory address space? Is there a FPGA device in it the controller?
This whole question may be wrong as Iack some knowledge about it.
This whole question may be wrong as Iack some knowledge about it.
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Hyeonggon Yoo
hyeyoo
Hmm what's the point of PCIe Root Complex-Integrated Endpoints (RCiEP) rather than Endpoints connected to Root Port
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Hyeonggon Yoo
hyeyoo
Edited 10 months ago
In the ACPI specification; the character representing ACPI root namespace ('\') seems to be escaped (' and \') and looks like this.
How have people been reading this?
How have people been reading this?
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Hyeonggon Yoo
hyeyoo
Edited 10 months ago
my keyboard is not responding until the kerenel is loaded. what's wrong I want uefi please
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Hyeonggon Yoo
hyeyoo
Edited 10 months ago
UEFI (Unified Extensible Firmware Interface) standard defines the interface between platform firmware and OS (loader). UEFI only standards the interface with the firmware, but its implementation follows the Platform Integration (PI) standard, not UEFI. UEFI completely replaces BIOS used in traditional IBM PC environments.
An OS loader reads information such as ACPI tables, memory maps, etc. through UEFI and passes it to OS, which then takes over control. Most of the services provided by UEFI, including the ACPI Table and Memory Map, are not accessible after OS loader calls the UEFI's Boot Service ExitBootServices().
Intel provides open source reference implementations of firmware that adhere to the UEFI standard called EDK 2. The firmware also implements PCI host bus controllers, bus drivers, and device drivers.
In order to add CXL memory to the memory map during system initialization, the firmware must have CXL support added so that you can set up a CXL host bridge, switch, and device at system initialization before OS has taken the control.
An OS loader reads information such as ACPI tables, memory maps, etc. through UEFI and passes it to OS, which then takes over control. Most of the services provided by UEFI, including the ACPI Table and Memory Map, are not accessible after OS loader calls the UEFI's Boot Service ExitBootServices().
Intel provides open source reference implementations of firmware that adhere to the UEFI standard called EDK 2. The firmware also implements PCI host bus controllers, bus drivers, and device drivers.
In order to add CXL memory to the memory map during system initialization, the firmware must have CXL support added so that you can set up a CXL host bridge, switch, and device at system initialization before OS has taken the control.
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Hyeonggon Yoo
hyeyoo
Edited 10 months ago
In ACPI-compatible OS environment, NUMA node of memory ranges and distance matrix between NUMA nodes are parsed from ACPI SRAT/SLIT tables and they are provided firmware.
ACPI HMAT describes latency/bandwidth characteristics.
CDAT is a set of registers in CXL that reports bandwidth/latency characteristics of CXL devices/switches. it is consumed by firmware to produce HMAT/SRAT tables.
ACPI HMAT describes latency/bandwidth characteristics.
CDAT is a set of registers in CXL that reports bandwidth/latency characteristics of CXL devices/switches. it is consumed by firmware to produce HMAT/SRAT tables.
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