Harry (Hyeonggon) Yoo
Posts
498Following
97Followers
113- Linux Kernel Developer @ Oracle (Linux Kernel MM) (2025.02 ~ Present)
- Reviewer for the Linux Slab & Reverse Mapping subsystem
- Former Intern @ NVIDIA, SK Hynix, Panmnesia (Security, MM and CXL)
- B.Sc. in Computer Science & Engineering, Chungnam National University (Class of 2025)
Opinions are my own.
My interests are:
Memory Management,
Computer Architecture,
Circuit Design,
Virtualization
Harry (Hyeonggon) Yoo
hyeyoo
@alphaville
Alternatively you can pretend to understand the Linux kernel
https://medium.com/@c0ngwang/how-to-pretend-to-be-a-linux-kernel-expert-b1ca21ac6384
Alternatively you can pretend to understand the Linux kernel
https://medium.com/@c0ngwang/how-to-pretend-to-be-a-linux-kernel-expert-b1ca21ac6384
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 1 year ago
A big barrier to reading and analyzing code is a psychological resistance to reading unfamiliar text
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@ptesarik Yeah it's quite confusing, at first attempt I searched with the keyword "DMA" and "Direct Memory Access" but couldn't find anything useful - because it's very natural for device to access memory (by becoming bus master)
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 1 year ago
TIL:
DMA in PCI(e) means a device initiates memory read/write transactions.
But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)
Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)
DMA in PCI(e) means a device initiates memory read/write transactions.
But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)
Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 1 year ago
It's already 1am but 3 hours left until CXL MC... uh, I'm tired
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Harry (Hyeonggon) Yoo
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James Bottomley
jejb@mastodon.online@linuxplumbersconf Youtube Live Stream URLs are now available on the Schedule Overview page (https://lpc.events/event/17/timetable/#all).
Find the track you want and click the paperclip on the upper right corner to bring up the Live Stream Link
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Harry (Hyeonggon) Yoo
hyeyoo
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 1 year ago
This winter I'm going to do a research project (for the first time in my life!) with other students, at Purdue University (Indiana).
2 months is bit short for a project, so we need to find a very small question that no one has answered.
It seems I've found a question suitable for our need in the compiler area, but I need to consult with the professor to verify if it's a valid question.
2 months is bit short for a project, so we need to find a very small question that no one has answered.
It seems I've found a question suitable for our need in the compiler area, but I need to consult with the professor to verify if it's a valid question.
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Harry (Hyeonggon) Yoo
hyeyoo
After 2 months of learning related stuffs I finally feel like I'm ready to dive into CXL device emulation code.
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 1 year ago
a foolish mistake: can't open my phone's card wallet because of the strap I bought yesterday...
Should've realized that I can't have both :(
Should've realized that I can't have both :(
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 1 year ago
There are two ways to access device registers in PCIe:
1) As an extended capability in PCIe extended configuration space, (Designated) Vendor-Specific Extended Capabilities can be used to access vendor-specific registers. As more than one vendor produces CXL devices, DVSEC is used instead of VSEC.
2) BARs can be used to map device resources (registers or memory) into system memory address space.
Errrr.. btw many registers are there in the CXL spec :/
Notably:
- (DVSEC) "PCIe DVSEC for CXL Device" is used to identify CXL-capable PCIe endpoints
- (DVSEC) "Register Locator DVSEC" is used to locate CXL memory-mapped registers
- (Memory-Mapped) "CXL 2.0 Component Registers" is used to configure CXL Components (Host Bridge, Root Port, Upstream/Downstream Port, Device)
- (Memory-Mapped) "CXL Device Register Interface" is used to access CXL device registers and issue commands to a CXL device
Configuration space of Every CXL 2.0 component can be accessed via the standard PCIe method, except Host Bridges. Component Registers of CXL Host Bridges are located by ACPI CEDT table, which also contains CFMWS (CXL Fixed-Memory-Window Structure).
1) As an extended capability in PCIe extended configuration space, (Designated) Vendor-Specific Extended Capabilities can be used to access vendor-specific registers. As more than one vendor produces CXL devices, DVSEC is used instead of VSEC.
2) BARs can be used to map device resources (registers or memory) into system memory address space.
Errrr.. btw many registers are there in the CXL spec :/
Notably:
- (DVSEC) "PCIe DVSEC for CXL Device" is used to identify CXL-capable PCIe endpoints
- (DVSEC) "Register Locator DVSEC" is used to locate CXL memory-mapped registers
- (Memory-Mapped) "CXL 2.0 Component Registers" is used to configure CXL Components (Host Bridge, Root Port, Upstream/Downstream Port, Device)
- (Memory-Mapped) "CXL Device Register Interface" is used to access CXL device registers and issue commands to a CXL device
Configuration space of Every CXL 2.0 component can be accessed via the standard PCIe method, except Host Bridges. Component Registers of CXL Host Bridges are located by ACPI CEDT table, which also contains CFMWS (CXL Fixed-Memory-Window Structure).
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Harry (Hyeonggon) Yoo
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Kees Cook (old account)
kees@fosstodon.orgHere's how to enable the kernel Memory Tagging Extension (#MTE) on the Pixel 8:
adb shell setprop arm64.memtag.bootctl memtag,memtag-kernel
I'm so happy there's real-world hardware finally available to provide mitigations against linear buffer overflows and many types of use-after-free flaws.
More details here:
https://outflux.net/blog/archives/2023/10/26/enable-mte-on-pixel-8/
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