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n00b Kernel Hacker
- Ex-Intern @ NVIDIA Korea (Security System Software) (2024.06-2024.11)
- Ex-Intern @ Panmneisa (CXL emulation stuff) (~2023.12)
- Undergraduate majoring CSE (estimated graduation: Feb. 2025)
- Working as reviewer at Linux Slab subsystem
- Born in August 6, 2000

Opinions are my own.

My interests are:
Memory Management,
Computer Architecture,
Circuit Design,
Virtualization
Edited 1 year ago
UEFI (Unified Extensible Firmware Interface) standard defines the interface between platform firmware and OS (loader). UEFI only standards the interface with the firmware, but its implementation follows the Platform Integration (PI) standard, not UEFI. UEFI completely replaces BIOS used in traditional IBM PC environments.

An OS loader reads information such as ACPI tables, memory maps, etc. through UEFI and passes it to OS, which then takes over control. Most of the services provided by UEFI, including the ACPI Table and Memory Map, are not accessible after OS loader calls the UEFI's Boot Service ExitBootServices().

Intel provides open source reference implementations of firmware that adhere to the UEFI standard called EDK 2. The firmware also implements PCI host bus controllers, bus drivers, and device drivers.

In order to add CXL memory to the memory map during system initialization, the firmware must have CXL support added so that you can set up a CXL host bridge, switch, and device at system initialization before OS has taken the control.
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Edited 1 year ago
In ACPI-compatible OS environment, NUMA node of memory ranges and distance matrix between NUMA nodes are parsed from ACPI SRAT/SLIT tables and they are provided firmware.

ACPI HMAT describes latency/bandwidth characteristics.

CDAT is a set of registers in CXL that reports bandwidth/latency characteristics of CXL devices/switches. it is consumed by firmware to produce HMAT/SRAT tables.
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Edited 1 year ago
why does raid1 rebuild take longer than it should
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UEFI/ACPI is killimg my brain
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Edited 1 year ago

NASA is sending a software update to the Voyager 2 spacecraft today!

Data will be sent at 16 bps with a 19 kW transmitter using the 70-m dish at DSN Canberra.
Distance: 20 billion km
Light travel time: 18:40 hours

The patch contains logic to recover from glitches similar to the one in May 2022, when the AACS system on Voyager 1 was sending garbled data. The root cause was not diagnosed. The patch will be activated on Oct 28. Voyager 2 will be next.

https://www.jpl.nasa.gov/news/nasas-voyager-team-focuses-on-software-patch-thrusters

1/n

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Edited 1 year ago
https://coverage.kerneltesting.org/slab-experimental-6283c415/mm/

This is a merged LCOV output of my mm & slab test coverage from 30 different kernel configurations.

Looks mostly fine but there are a few small problems:
- Sometimes numbers are inconsistent
- Omission of (some) inline function coverage
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Edited 1 year ago
@cwayne I'm consistently surpressing my urge to shitpost on your regular LinkedIn posts, phew...
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Edited 1 year ago
I need to learn Ansible instead of writing non-portable scripts and memorizing all of them
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A LKML thread meme summary, pure shitposting because SCNR, not meant as an endorsement nor ridicule of any side
Show content
STOP DOING MSEAL()

SYSCALLS WERE NOT SUPPOSED TO BE GIVEN MM_SEAL_ FLAGS

YEARS OF MINMUTABLE() yet NO REAL-WORLD USE FOUND for using more than addr, len PARAMETERS

Wanted not to bother with that anyway to get a break? We had a tool for that: It was called "LD.SO"

"one place honors the sealing, random other places do not" - Statements dreamed up by the utterly Deranged.

LOOK at what Chrome has been demanding your Support for all this time, with all the mprotect(2) permission reduction & OPENBSD_MUTABLE we built for them.
(This is REAL Code, done by REAL Kernel developers).

ON_BEHALF_OF_KERNEL ?????

ON_BEHALF_OF_USERSPACE ???????

VM_SEAL_* -> MM_SEAL_* -> MM_ACTION_* ?????????????????

"Hello, I would like a MM_SEAL_MUNMAP but not MM_SEAL_MMAP VMA please."

They have played us for absolute fools
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Edited 1 year ago
This is how a silently enabled kernel configuration can affect your system performance:

https://lore.kernel.org/stable/97397e8d-f447-4cf7-84a1-070989d0a7fd@amazon.com/T/#u

I fixed this at the beginning of this year, but did not backport to stable trees. Luiz Capitulino from Amazon reported that this resulted in performance regression in their 6.1 kernels.

DEBUG_PREEMPT has been enabled by default since pre-git era for PREEMPT kernels, but distros that were using PREEMPT_VOLUNTARY silently enabled PREEMPTION and DEBUG_PREEMPT after the introduction of PREEMPT_DYNAMIC. And DEBUG_PREEMPT is better disabled for production kernels regardless of the preemption model used.
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Why are gcov/lcov/genhtml so sensitive to source code path :(

lcov/genhtml requires that there should be source code in the exactly same path of source code in the build machine.
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Errr.... IDK why people contact me via Linkedin asking 'Is your company willing to by hardware from us?'

I DON'T KNOW I AM AN INTERN :(
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Edited 1 year ago
https://it.chosun.com/news/articleView.html?idxno=2023092102422

...Linux for Desktop opens new world...
...New opportunity for Korean OS in goverment PCs...

https://www.hancom.com/product/productGooroomMain.do

...Goorm OS provides secure, convenient, unique experience to desktop users...
...Goorm OS is based on debian linux...


Seriously?

I'm tired of fancy new Korea's OS platforms (K-OS) which is either 1) just another Linux distribution or 2) not Linux based but being so unusable
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Edited 1 year ago

Windows: 0
Linux: 1

It is not Linux's job to stop you from shooting your foot. If you so choose to do so, then it is Linux's job to deliver Mr. Bullet to Mr. Foot in the most efficient way it knows.

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Hmm when running builds and testcases, my machine sometimes becomes very unstable and stuck for a while.

this causes some build/test failures because git clone or job submit timeouts are exceeded.

it's very annoying and I need to fix, but I couldn't find out why. I need to setup a monitoring system...
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first time using GCOV, it's pretty nice.
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Edited 1 year ago
now I'm slowly getting how CXL manages cache coherence of device memory (HDM-{H,D,DB}). my head aches.

BTW this is a good material to grasp some important concepts of of CXL.

https://arxiv.org/abs/2306.11227

Even if it's not the final version yet.
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Edited 1 year ago
progress of this week:

#kerneltesting side project

Now my testing system can submit and run LAVA [1] test jobs automatically after jenkins [2] build!

[1] https://lava.kerneltesting.org/scheduler/alljobs
[2] https://jenkins.kerneltesting.org/job/slab/

currently it runs those:
- a subset of mm LTP testcases
- hackbench for a very short time
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Edited 1 year ago
```
As a bit of history, in the early days of PCI the spec writers anticipated cases
where PCI would actually replace the processor bus.
```
from "PCI Express Technology 3.0", MindShare

And yeah, that seems to be revived in 2019 by Intel, in the name of IAL (Intel Accelerator Link), which was renamed to CXL (Compute Express Link) later. The main reason why Intel donated IAL was to avoid making the industry fragmented. Later CXL consortium was founded and over 250 companies now contribute to the specification. Including my company! (who hired me as an intern)
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