Hyeonggon Yoo
Posts
469Following
90Followers
94- Intern @ NVIDIA Korea (Security System Software) (2024.06 ~)
- Ex-Intern @ Panmneisa (CXL emulation stuff) (~2023.12)
- Undergraduate majoring CSE (estimated graduation: Feb. 2025)
- Working as reviewer at Linux Slab subsystem
- Born in August 6, 2000
Opinions are my own.
My interests are:
Memory Management,
Computer Architecture,
Circuit Design,
Virtualization
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@vbabka
Designing VIPT caches where size/associativity <= PAGE_SIZE is a way to avoid the synonym problem, no?
It gets tricky when size/associativity > PAGE_SIZE and it seems both Intel and ARM have patents to deal with it
https://patents.google.com/patent/US11314647B2/en
https://patents.google.com/patent/US20070033318A1/en
Designing VIPT caches where size/associativity <= PAGE_SIZE is a way to avoid the synonym problem, no?
It gets tricky when size/associativity > PAGE_SIZE and it seems both Intel and ARM have patents to deal with it
https://patents.google.com/patent/US11314647B2/en
https://patents.google.com/patent/US20070033318A1/en
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Hyeonggon Yoo
hyeyoo
The traditional Korean age system has been retired in South Korea, and now we use the international standard aging system.
I was 24 in the Korean age system, but now I'm legally 22 :P
https://www.bbc.com/news/world-asia-63903771
I was 24 in the Korean age system, but now I'm legally 22 :P
https://www.bbc.com/news/world-asia-63903771
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Hyeonggon Yoo
hyeyoo
still haven't recovered from jet lag (?) from the final exam period. today went to bed at 11 PM, woke up at 2 AM, and it's now 6 AM.
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
sometimes wanna stop posting normally and just shitpost all the time
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Hyeonggon Yoo
hyeyoo
Edited 1 year ago
started wondering where it's documented that x86 processors deal with the synonym problem, as they use VIPT data caches.
on ARMv8 processors there is an architectural guarantee that data caches acts as PIPT cache even if it's actually VIPT, so it's guaranteed not to suffer from D-cache aliasing.
I've been heard that there is a similar guarantee on x86 processors but haven't found any official references about it - errr, I guess it's time to read some part of the intel manual.
btw this is quite old but is very nice introduction:
https://www.linuxjournal.com/article/7105
on ARMv8 processors there is an architectural guarantee that data caches acts as PIPT cache even if it's actually VIPT, so it's guaranteed not to suffer from D-cache aliasing.
I've been heard that there is a similar guarantee on x86 processors but haven't found any official references about it - errr, I guess it's time to read some part of the intel manual.
btw this is quite old but is very nice introduction:
https://www.linuxjournal.com/article/7105
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@ljs @kernellogger @sj
Ah, I added sj because IIRC he's planning implement an auto tuner for DAMON parameters - no one should be like "bpftune can tune everything and make more parameters"
it would have been horrible if i.e. active/inactive list balancing was implemented as a kernel parameter :P
Ah, I added sj because IIRC he's planning implement an auto tuner for DAMON parameters - no one should be like "bpftune can tune everything and make more parameters"
it would have been horrible if i.e. active/inactive list balancing was implemented as a kernel parameter :P
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@kernellogger
@sj you might be interested in adapting DAMON parameters?
btw I wonder how broad range of parameters could be covered
@sj you might be interested in adapting DAMON parameters?
btw I wonder how broad range of parameters could be covered
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