Harry (Hyeonggon) Yoo
Posts
576Following
104Followers
118- Linux Kernel Developer @ Oracle (Linux Kernel MM) (2025.02 ~ Present)
- Reviewer for the Linux Slab & Reverse Mapping subsystem
- Former Intern @ NVIDIA, SK Hynix, Panmnesia (Security, MM and CXL)
- B.Sc. in Computer Science & Engineering, Chungnam National University (Class of 2025)
Opinions are my own.
My interests are:
Memory Management,
Computer Architecture,
Circuit Design,
Virtualization
Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
a foolish mistake: can't open my phone's card wallet because of the strap I bought yesterday...
Should've realized that I can't have both :(
Should've realized that I can't have both :(
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
There are two ways to access device registers in PCIe:
1) As an extended capability in PCIe extended configuration space, (Designated) Vendor-Specific Extended Capabilities can be used to access vendor-specific registers. As more than one vendor produces CXL devices, DVSEC is used instead of VSEC.
2) BARs can be used to map device resources (registers or memory) into system memory address space.
Errrr.. btw many registers are there in the CXL spec :/
Notably:
- (DVSEC) "PCIe DVSEC for CXL Device" is used to identify CXL-capable PCIe endpoints
- (DVSEC) "Register Locator DVSEC" is used to locate CXL memory-mapped registers
- (Memory-Mapped) "CXL 2.0 Component Registers" is used to configure CXL Components (Host Bridge, Root Port, Upstream/Downstream Port, Device)
- (Memory-Mapped) "CXL Device Register Interface" is used to access CXL device registers and issue commands to a CXL device
Configuration space of Every CXL 2.0 component can be accessed via the standard PCIe method, except Host Bridges. Component Registers of CXL Host Bridges are located by ACPI CEDT table, which also contains CFMWS (CXL Fixed-Memory-Window Structure).
1) As an extended capability in PCIe extended configuration space, (Designated) Vendor-Specific Extended Capabilities can be used to access vendor-specific registers. As more than one vendor produces CXL devices, DVSEC is used instead of VSEC.
2) BARs can be used to map device resources (registers or memory) into system memory address space.
Errrr.. btw many registers are there in the CXL spec :/
Notably:
- (DVSEC) "PCIe DVSEC for CXL Device" is used to identify CXL-capable PCIe endpoints
- (DVSEC) "Register Locator DVSEC" is used to locate CXL memory-mapped registers
- (Memory-Mapped) "CXL 2.0 Component Registers" is used to configure CXL Components (Host Bridge, Root Port, Upstream/Downstream Port, Device)
- (Memory-Mapped) "CXL Device Register Interface" is used to access CXL device registers and issue commands to a CXL device
Configuration space of Every CXL 2.0 component can be accessed via the standard PCIe method, except Host Bridges. Component Registers of CXL Host Bridges are located by ACPI CEDT table, which also contains CFMWS (CXL Fixed-Memory-Window Structure).
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Harry (Hyeonggon) Yoo
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Kees Cook (old account)
kees@fosstodon.orgHere's how to enable the kernel Memory Tagging Extension (#MTE) on the Pixel 8:
adb shell setprop arm64.memtag.bootctl memtag,memtag-kernel
I'm so happy there's real-world hardware finally available to provide mitigations against linear buffer overflows and many types of use-after-free flaws.
More details here:
https://outflux.net/blog/archives/2023/10/26/enable-mte-on-pixel-8/
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Harry (Hyeonggon) Yoo
hyeyoo
I have a thing (wanna do at some point in my life) for designing processors, memory modules and neuromorphic processors
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
Why do we have two different specifications about firmware interface (UEFI and ACPI)?
Why can't UEFI (Unified EFI) unify everything :/
Why can't UEFI (Unified EFI) unify everything :/
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
How do memory controllers "map" device resources (memory or registers) with address spaces assigned via PCI BARs into system memory address space? Is there a FPGA device in it the controller?
This whole question may be wrong as Iack some knowledge about it.
This whole question may be wrong as Iack some knowledge about it.
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Harry (Hyeonggon) Yoo
hyeyoo
Hmm what's the point of PCIe Root Complex-Integrated Endpoints (RCiEP) rather than Endpoints connected to Root Port
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
In the ACPI specification; the character representing ACPI root namespace ('\') seems to be escaped (' and \') and looks like this.
How have people been reading this?
How have people been reading this?
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
my keyboard is not responding until the kerenel is loaded. what's wrong I want uefi please
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
UEFI (Unified Extensible Firmware Interface) standard defines the interface between platform firmware and OS (loader). UEFI only standards the interface with the firmware, but its implementation follows the Platform Integration (PI) standard, not UEFI. UEFI completely replaces BIOS used in traditional IBM PC environments.
An OS loader reads information such as ACPI tables, memory maps, etc. through UEFI and passes it to OS, which then takes over control. Most of the services provided by UEFI, including the ACPI Table and Memory Map, are not accessible after OS loader calls the UEFI's Boot Service ExitBootServices().
Intel provides open source reference implementations of firmware that adhere to the UEFI standard called EDK 2. The firmware also implements PCI host bus controllers, bus drivers, and device drivers.
In order to add CXL memory to the memory map during system initialization, the firmware must have CXL support added so that you can set up a CXL host bridge, switch, and device at system initialization before OS has taken the control.
An OS loader reads information such as ACPI tables, memory maps, etc. through UEFI and passes it to OS, which then takes over control. Most of the services provided by UEFI, including the ACPI Table and Memory Map, are not accessible after OS loader calls the UEFI's Boot Service ExitBootServices().
Intel provides open source reference implementations of firmware that adhere to the UEFI standard called EDK 2. The firmware also implements PCI host bus controllers, bus drivers, and device drivers.
In order to add CXL memory to the memory map during system initialization, the firmware must have CXL support added so that you can set up a CXL host bridge, switch, and device at system initialization before OS has taken the control.
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
In ACPI-compatible OS environment, NUMA node of memory ranges and distance matrix between NUMA nodes are parsed from ACPI SRAT/SLIT tables and they are provided firmware.
ACPI HMAT describes latency/bandwidth characteristics.
CDAT is a set of registers in CXL that reports bandwidth/latency characteristics of CXL devices/switches. it is consumed by firmware to produce HMAT/SRAT tables.
ACPI HMAT describes latency/bandwidth characteristics.
CDAT is a set of registers in CXL that reports bandwidth/latency characteristics of CXL devices/switches. it is consumed by firmware to produce HMAT/SRAT tables.
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
why does raid1 rebuild take longer than it should
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Harry (Hyeonggon) Yoo
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AkaSci 🛰️
AkaSci@fosstodon.org
Edited 2 years ago
NASA is sending a software update to the Voyager 2 spacecraft today!
Data will be sent at 16 bps with a 19 kW transmitter using the 70-m dish at DSN Canberra.
Distance: 20 billion km
Light travel time: 18:40 hours
The patch contains logic to recover from glitches similar to the one in May 2022, when the AACS system on Voyager 1 was sending garbled data. The root cause was not diagnosed. The patch will be activated on Oct 28. Voyager 2 will be next.
https://www.jpl.nasa.gov/news/nasas-voyager-team-focuses-on-software-patch-thrusters
#Voyager
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
https://coverage.kerneltesting.org/slab-experimental-6283c415/mm/
This is a merged LCOV output of my mm & slab test coverage from 30 different kernel configurations.
Looks mostly fine but there are a few small problems:
- Sometimes numbers are inconsistent
- Omission of (some) inline function coverage
This is a merged LCOV output of my mm & slab test coverage from 30 different kernel configurations.
Looks mostly fine but there are a few small problems:
- Sometimes numbers are inconsistent
- Omission of (some) inline function coverage
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
I need to learn Ansible instead of writing non-portable scripts and memorizing all of them
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Harry (Hyeonggon) Yoo
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A LKML thread meme summary, pure shitposting because SCNR, not meant as an endorsement nor ridicule of any side
Show content
STOP DOING MSEAL()
SYSCALLS WERE NOT SUPPOSED TO BE GIVEN MM_SEAL_ FLAGS
YEARS OF MINMUTABLE() yet NO REAL-WORLD USE FOUND for using more than addr, len PARAMETERS
Wanted not to bother with that anyway to get a break? We had a tool for that: It was called "LD.SO"
"one place honors the sealing, random other places do not" - Statements dreamed up by the utterly Deranged.
LOOK at what Chrome has been demanding your Support for all this time, with all the mprotect(2) permission reduction & OPENBSD_MUTABLE we built for them.
(This is REAL Code, done by REAL Kernel developers).
ON_BEHALF_OF_KERNEL ?????
ON_BEHALF_OF_USERSPACE ???????
VM_SEAL_* -> MM_SEAL_* -> MM_ACTION_* ?????????????????
"Hello, I would like a MM_SEAL_MUNMAP but not MM_SEAL_MMAP VMA please."
They have played us for absolute fools
SYSCALLS WERE NOT SUPPOSED TO BE GIVEN MM_SEAL_ FLAGS
YEARS OF MINMUTABLE() yet NO REAL-WORLD USE FOUND for using more than addr, len PARAMETERS
Wanted not to bother with that anyway to get a break? We had a tool for that: It was called "LD.SO"
"one place honors the sealing, random other places do not" - Statements dreamed up by the utterly Deranged.
LOOK at what Chrome has been demanding your Support for all this time, with all the mprotect(2) permission reduction & OPENBSD_MUTABLE we built for them.
(This is REAL Code, done by REAL Kernel developers).
ON_BEHALF_OF_KERNEL ?????
ON_BEHALF_OF_USERSPACE ???????
VM_SEAL_* -> MM_SEAL_* -> MM_ACTION_* ?????????????????
"Hello, I would like a MM_SEAL_MUNMAP but not MM_SEAL_MMAP VMA please."
They have played us for absolute fools
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