Harry (Hyeonggon) Yoo
Posts
566Following
104Followers
116- Linux Kernel Developer @ Oracle (Linux Kernel MM) (2025.02 ~ Present)
- Reviewer for the Linux Slab & Reverse Mapping subsystem
- Former Intern @ NVIDIA, SK Hynix, Panmnesia (Security, MM and CXL)
- B.Sc. in Computer Science & Engineering, Chungnam National University (Class of 2025)
Opinions are my own.
My interests are:
Memory Management,
Computer Architecture,
Circuit Design,
Virtualization
Harry (Hyeonggon) Yoo
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Edited 2 years ago
OK, enough joking, time to get serious now https://lore.kernel.org/all/20231113191340.17482-22-vbabka@suse.cz/T/
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
there are so many batteries I should charge everyday... laptop, smartphone, smart watch and bluetooth earphones.
start to feel nervous when one of them is gone.
start to feel nervous when one of them is gone.
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Harry (Hyeonggon) Yoo
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K. Ryabitsev 🍁
monsieuricon
So, you want to read LKML with Gmail (experimental, testers needed)
https://lore.kernel.org/workflows/20231115-black-partridge-of-growth-54bf2e@nitro/
https://lore.kernel.org/workflows/20231115-black-partridge-of-growth-54bf2e@nitro/
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Harry (Hyeonggon) Yoo
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LWN.net is now @LWN@lwn.net
LWN@fosstodon.org[$] Faster kernel testing with virtme-ng https://lwn.net/Articles/951313/ #LWN
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Harry (Hyeonggon) Yoo
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
A few diagrams about PCIe. 1) An example PCIe topology 2) PCIe Switch and 3) Root Complex
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Harry (Hyeonggon) Yoo
hyeyoo
what, there's a script to import linux kernel headers to QEMU.
From commit 412a8245 ("pci_regs.h: import from linux"):
```
It seems to make sense to import pci_regs.h from linux: why maintain our own?
As a first step, move the header to standard-headers, and add it to the update script.
```
From commit 412a8245 ("pci_regs.h: import from linux"):
```
It seems to make sense to import pci_regs.h from linux: why maintain our own?
As a first step, move the header to standard-headers, and add it to the update script.
```
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Harry (Hyeonggon) Yoo
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Paul Moore
securepaul@fosstodon.orgI'm a little surprised and disappointed that the 2023 Linux Foundation TAB election only has five candidates running for the five open seats. All five of the candidates are existing TAB members.
It would seem like one of the issues the TAB should focus on this year is getting more people interested in TAB participation.
https://lore.kernel.org/lkml/e851a8e5-c4c2-4b5d-887a-509e591cff49@intel.com
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
A big barrier to reading and analyzing code is a psychological resistance to reading unfamiliar text
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
TIL:
DMA in PCI(e) means a device initiates memory read/write transactions.
But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)
Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)
DMA in PCI(e) means a device initiates memory read/write transactions.
But how to make a device initiate such a transaction is device-specific (i.e. a device implements a DMA command via its registers)
Wondering if a DMA interface can be added to CXL.io protocol so that page migrations can be done in a peer-to-peer manner without host interference. (in systems with multiple memory tiers)
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
It's already 1am but 3 hours left until CXL MC... uh, I'm tired
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Harry (Hyeonggon) Yoo
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James Bottomley
jejb@mastodon.online@linuxplumbersconf Youtube Live Stream URLs are now available on the Schedule Overview page (https://lpc.events/event/17/timetable/#all).
Find the track you want and click the paperclip on the upper right corner to bring up the Live Stream Link
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
This winter I'm going to do a research project (for the first time in my life!) with other students, at Purdue University (Indiana).
2 months is bit short for a project, so we need to find a very small question that no one has answered.
It seems I've found a question suitable for our need in the compiler area, but I need to consult with the professor to verify if it's a valid question.
2 months is bit short for a project, so we need to find a very small question that no one has answered.
It seems I've found a question suitable for our need in the compiler area, but I need to consult with the professor to verify if it's a valid question.
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Harry (Hyeonggon) Yoo
hyeyoo
After 2 months of learning related stuffs I finally feel like I'm ready to dive into CXL device emulation code.
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
a foolish mistake: can't open my phone's card wallet because of the strap I bought yesterday...
Should've realized that I can't have both :(
Should've realized that I can't have both :(
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Harry (Hyeonggon) Yoo
hyeyoo
Edited 2 years ago
There are two ways to access device registers in PCIe:
1) As an extended capability in PCIe extended configuration space, (Designated) Vendor-Specific Extended Capabilities can be used to access vendor-specific registers. As more than one vendor produces CXL devices, DVSEC is used instead of VSEC.
2) BARs can be used to map device resources (registers or memory) into system memory address space.
Errrr.. btw many registers are there in the CXL spec :/
Notably:
- (DVSEC) "PCIe DVSEC for CXL Device" is used to identify CXL-capable PCIe endpoints
- (DVSEC) "Register Locator DVSEC" is used to locate CXL memory-mapped registers
- (Memory-Mapped) "CXL 2.0 Component Registers" is used to configure CXL Components (Host Bridge, Root Port, Upstream/Downstream Port, Device)
- (Memory-Mapped) "CXL Device Register Interface" is used to access CXL device registers and issue commands to a CXL device
Configuration space of Every CXL 2.0 component can be accessed via the standard PCIe method, except Host Bridges. Component Registers of CXL Host Bridges are located by ACPI CEDT table, which also contains CFMWS (CXL Fixed-Memory-Window Structure).
1) As an extended capability in PCIe extended configuration space, (Designated) Vendor-Specific Extended Capabilities can be used to access vendor-specific registers. As more than one vendor produces CXL devices, DVSEC is used instead of VSEC.
2) BARs can be used to map device resources (registers or memory) into system memory address space.
Errrr.. btw many registers are there in the CXL spec :/
Notably:
- (DVSEC) "PCIe DVSEC for CXL Device" is used to identify CXL-capable PCIe endpoints
- (DVSEC) "Register Locator DVSEC" is used to locate CXL memory-mapped registers
- (Memory-Mapped) "CXL 2.0 Component Registers" is used to configure CXL Components (Host Bridge, Root Port, Upstream/Downstream Port, Device)
- (Memory-Mapped) "CXL Device Register Interface" is used to access CXL device registers and issue commands to a CXL device
Configuration space of Every CXL 2.0 component can be accessed via the standard PCIe method, except Host Bridges. Component Registers of CXL Host Bridges are located by ACPI CEDT table, which also contains CFMWS (CXL Fixed-Memory-Window Structure).
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